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    Switching circuit avoiding glitches at the instant of switch-over between two clock signals
    2.
    发明授权
    Switching circuit avoiding glitches at the instant of switch-over between two clock signals 失效
    开关电路在两个时钟信号之间切换瞬间避免毛刺

    公开(公告)号：US4855615A

    公开(公告)日：1989-08-08

    申请号：US62158

    申请日：1987-06-12

    申请人： Richard J. Humpleman

    发明人： Richard J. Humpleman

    IPC分类号： H03K17/00 ,  G04G3/00 ,  H04L7/00

    CPC分类号： G04G3/00 ,  H04L7/0083

    摘要： A switching circuit is described, for selecting between first and second clock signals. When it is desired to switch from the first to the second clock signal, the first clock signal is de-selected in synchronism with the beat of the first clock and then, after a delay, the second clock signal is selected in synchronism with the beat of the second clock. Conversely, when it is desired to switch from the second to the first clock signal, the second clock signal is de-selected in synchronism with the beat of the second clock and then, after a delay, the first clock signal is selected in synchronism with the beat of the first clock. This avoids the possibility of a short pulse or "glitch" at the instant of switch-over.

    摘要翻译： 描述了用于在第一和第二时钟信号之间进行选择的开关电路。 当期望从第一时钟信号切换到第二时钟信号时，第一时钟信号与第一时钟的拍频同步地被取消选择，然后在延迟之后，与拍子同步地选择第二时钟信号 的第二个时钟。 相反，当希望从第二时钟信号切换到第一时钟信号时，第二时钟信号与第二时钟的脉冲同步地被选择，然后在延迟之后，与第一时钟信号同步地选择第一时钟信号 第一时钟的节拍。 这避免了在切换瞬间发生短脉冲或“毛刺”的可能性。

    Clock/data synchronization interface apparatus and method
    3.
    发明授权
    Clock/data synchronization interface apparatus and method 失效
    时钟/数据同步接口设备和方法

    公开(公告)号：US4691294A

    公开(公告)日：1987-09-01

    申请号：US776823

    申请日：1985-09-17

    申请人： Richard J. Humpleman

    发明人： Richard J. Humpleman

    IPC分类号： G06F13/42 ,  G06F13/00

    CPC分类号： G06F13/423

    摘要： In order to synchronize data signals transferred from a source unit to a destination unit, a clock signal is transmitted from the destination unit to the source unit and transmission of data is effected under control of the received clock signal. The received clock signal is retransmitted back to the destination unit with the trasmitted data and is used to register receipt of the data.

    摘要翻译： 为了使从源单元传送到目的地单元的数据信号同步，从目的地单元发送时钟信号到源单元，并且在接收到的时钟信号的控制下进行数据传输。 接收到的时钟信号被重发回目的地单元，并且用于记录数据的接收。

    Parallel-to-serial converter
    4.
    发明授权
    Parallel-to-serial converter 失效
    并行到串行转换器

    公开(公告)号：US4759042A

    公开(公告)日：1988-07-19

    申请号：US23416

    申请日：1987-03-09

    申请人： Richard J. Humpleman

    发明人： Richard J. Humpleman

    IPC分类号： H03M9/00 ,  G11C7/00 ,  G11C15/00

    CPC分类号： H03M9/00

    摘要： A parallel-to-serial converter is described, comprising a shift register into which a data word can be loaded in parallel and then shifted out serially. As the data is shifted out, a string of zeros is shifted in. When a predetermined number of zeros is detected, a flip-flop is set at the next clock beat. This switches the shift register into its parallel load mode so that, at the next again clock beat the shift register is parallel loaded with the next data word. The detection of the predetermined number of zeros and the setting up of the shift register occur in different clock periods, allowing the clock period to be reduced, thus increasing the speed of operation.

    摘要翻译： 描述了并行到串行转换器，包括一个移位寄存器，数据字可并行加载到该移位寄存器中，然后串行移出。 当数据被移出时，一串零被移入。当检测到预定数量的零时，触发器被设置在下一个时钟节拍。 这样就将移位寄存器切换到并行负载模式，这样在下一个时钟脉冲下，移位寄存器被并行加载下一个数据字。 预定数量的零的检测和移位寄存器的设置发生在不同的时钟周期中，从而允许减少时钟周期，从而提高操作速度。