公开(公告)号：US06576548B1

公开(公告)日：2003-06-10

申请号：US10079861

申请日：2002-02-22

申请人： Amy Tu ,  Minh Van Ngo ,  Austin Frenkel ,  Robert J. Chiu ,  Jeff Erhardt

发明人： Amy Tu ,  Minh Van Ngo ,  Austin Frenkel ,  Robert J. Chiu ,  Jeff Erhardt

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/31105 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76877

摘要： Reliable contacts/vias are formed by sputter etching to flare exposed edges of an opening formed in a dielectric layer, depositing a composite barrier layer and then filling the opening with tungsten at a low deposition rate. The resulting contact/via exhibits significantly reduced porosity and contact resistance. Embodiments include sputter etching to incline the edges of an opening formed in an oxide dielectric layer, e.g., a silicon oxide derived from TEOS or BPSG, at an angle of about 83° to about 86°, depositing a thin layer of Ti, e.g., at a thickness of about 250 Å to about 350 Å, depositing at least one layer of titanium nitride, e.g., three layers of titanium nitride, at a total thickness of about 130 Å to about 170 Å, and then depositing tungsten at a deposition rate of about 1,900 to about 2,300 Å/min to fill the opening.

摘要翻译： 通过溅射蚀刻形成可靠的触点/通孔，以对形成在电介质层中的开口的暴露边缘进行曝光，沉积复合阻挡层，然后以低沉积速率用钨填充开口。 所得到的接触/通孔显示出显着降低的孔隙率和接触电阻。 实施例包括溅射蚀刻，以约83°至约86°的角度倾斜形成在氧化物电介质层中的开口的边缘，例如衍生自TEOS或BPSG的氧化硅，沉积Ti薄层， 在约250埃至大约350埃的厚度上沉积至少一层氮化钛，例如三层氮化钛，总厚度为约至约为170埃，然后以沉积速率沉积钨 约1,900至约2,300埃/分钟以填充开口。

公开(公告)号：US06513151B1

公开(公告)日：2003-01-28

申请号：US09794503

申请日：2001-02-26

申请人： Jeff Erhardt ,  Khoi Phan

发明人： Jeff Erhardt ,  Khoi Phan

IPC分类号： G06F1750

CPC分类号： G03F7/70558 ,  G03F7/70625 ,  G03F7/70641 ,  G03F7/7065 ,  G03F7/70658

摘要： A method for new product mask evaluation is provided. Focus exposure matrices are printed at one or more layers (e.g., active gate) on full flow production wafers. The focus exposure matrices are then analyzed to produce data that facilitates detecting printed defects. The full flow production wafers are also subjected to end of line electrical testing to determine bit level errors. Print defects can be correlated with bit level errors to increase confidence in detected defects. The method includes a hierarchy of testing layers, each of which produce data that can be employed in detecting defects in a reticle and/or producing a yield analysis. The method involves scanning a reticle upon which the new product mask is etched and performing a printability simulation to determine what affect, if any, detected reticle defects will have on printing defects on a wafer. After the reticle is scanned, full flow production wafers printed from the pattern on the reticle can be scanned for defects, as can resist-on-silicon flat test wafers, where a higher signal to noise ratio facilitates detecting defects that may otherwise not be detected. The reticle scanning can include critical dimension measuring by scanning electron microscopy means and/or scatterometry means.

摘要翻译： 提供了一种新产品面膜评估方法。 在全流动生产晶片上的一个或多个层（例如，有源栅极）上印刷聚焦曝光矩阵。 然后分析焦点曝光矩阵以产生便于检测印刷缺陷的数据。 全流程生产晶片也经受终端电测试以确定位电平误差。 打印缺陷可以与位级错误相关联，以增加对检测到的缺陷的置信度。 该方法包括测试层的层级，每层测试层产生可用于检测掩模版中的缺陷和/或产生产量分析的数据。 该方法涉及扫描其上蚀刻了新产品掩模的掩模版并执行可印刷性模拟以确定检测到的掩模版缺陷对于在晶片上的印刷缺陷将产生什么影响（如果有的话）。 在掩模版被扫描之后，从掩模版上的图案印刷的全流动生产晶片可以被扫描以获得缺陷，如在硅平坦测试晶片上，其中更高的信噪比便于检测否则不能检测到的缺陷 。 掩模版扫描可以包括通过扫描电子显微镜装置和/或散射测量装置的临界尺寸测量。

公开(公告)号：US06613500B1

公开(公告)日：2003-09-02

申请号：US09824079

申请日：2001-04-02

申请人： Khoi A. Phan ,  Bhanwar Singh ,  Ramkumar Subramanian ,  Michael K. Templeton ,  Jeff Erhardt

发明人： Khoi A. Phan ,  Bhanwar Singh ,  Ramkumar Subramanian ,  Michael K. Templeton ,  Jeff Erhardt

IPC分类号： G03F700

CPC分类号： G03F7/70425 ,  G03F7/2022 ,  G03F7/203 ,  G03F7/70466

摘要： One aspect of the present invention relates to a method for reducing resist residue defects on a wafer structure. The method involves providing a semiconductor structure having a photoresist, the photoresist comprising open areas and circuit areas thereon; irradiating the open areas and circuit areas through a first photomask with a first energy dose to effect an image-wise pattern in the photoresist; irradiating the open areas of the photoresist through a second photomask with a second energy dose; and developing the photoresist.

摘要翻译： 本发明的一个方面涉及减少晶片结构上的抗蚀剂残留缺陷的方法。 该方法包括提供具有光致抗蚀剂的半导体结构，光致抗蚀剂包括开放区域和其上的电路区域; 通过具有第一能量剂量的第一光掩模照射开放区域和电路区域以在光致抗蚀剂中实现成像图案; 通过具有第二能量剂量的第二光掩模照射光致抗蚀剂的开放区域; 并显影光致抗蚀剂。

公开(公告)号：US06514859B1

公开(公告)日：2003-02-04

申请号：US09733843

申请日：2000-12-08

申请人： Jeff Erhardt ,  Eric Paton

发明人： Jeff Erhardt ,  Eric Paton

IPC分类号： H01L2144

CPC分类号： H01L29/66507 ,  H01L21/28518 ,  H01L29/4933

摘要： A method of forming a self-aligned silicide (salicide) with a double gate silicide. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area which is advantageously thicker than silicide formations over the source and drain areas.

摘要翻译： 用双栅极硅化​​物形成自对准硅化物（自对准硅化物）的方法。 该方法通过降低源极和漏极区域中的漏电流并降低栅极的多晶硅片电阻来提高晶体管的速度。 作为本方法的一个实施例的结果，在栅极区域上形成硅化物，其优选在源极和漏极区域上比硅化物层更厚。

公开(公告)号：US06521501B1

公开(公告)日：2003-02-18

申请号：US09310170

申请日：1999-05-11

申请人： Jeff Erhardt ,  Bin Yu ,  G. Jonathan Kluth

发明人： Jeff Erhardt ,  Bin Yu ,  G. Jonathan Kluth

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/324 ,  H01L29/6659

摘要： A method of forming a CMOS structure, the method including the acts of: forming a gate structure over a substrate layer; forming a silicide layer over the substrate layer; forming shallow source/drain areas in the substrate layer; forming an oxide diffusion barrier layer over the structure; forming a metal absorption layer over the oxide diffusion barrier layer; and melting portions of the substrate layer directly overlying the shallow source/drain areas, thereby transforming the shallow source/drain areas into shallow source/drain regions. The act of melting includes the act of exposing the metal absorption layer to pulsed laser beams.

摘要翻译： 一种形成CMOS结构的方法，所述方法包括以下动作：在衬底层上形成栅极结构; 在衬底层上形成硅化物层; 在衬底层中形成浅的源极/漏极区域; 在所述结构上形成氧化物扩散阻挡层; 在所述氧化物扩散阻挡层上形成金属吸收层; 并且将衬底层的部分直接覆盖在浅源极/漏极区域上，从而将浅的源极/漏极区域变换成浅的源极/漏极区域。 熔化的行为包括将金属吸收层暴露于脉冲激光束的行为。

公开(公告)号：US06399467B1

公开(公告)日：2002-06-04

申请号：US09733779

申请日：2000-12-08

申请人： Jeff Erhardt ,  Eric Paton

发明人： Jeff Erhardt ,  Eric Paton

IPC分类号： H01L213205

CPC分类号： H01L29/66507 ,  H01L21/28052 ,  H01L21/28518

摘要： A method of forming a self-aligned silicide (salicide) with a screening oxide. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area which is advantageously about two to three times thicker than silicide formations over the source and drain areas.

摘要翻译： 用筛选氧化物形成自对准硅化物（自对准硅化物）的方法。 该方法通过降低源极和漏极区域中的漏电流并降低栅极的多晶硅片电阻来提高晶体管的速度。 作为本方法的一个实施例的结果，在栅极区域上形成硅化物，其优选在源极和漏极区域上比硅化物层厚约2至3倍。

公开(公告)号：US06387786B1

公开(公告)日：2002-05-14

申请号：US09733778

申请日：2000-12-08

申请人： Jeff Erhardt ,  Eric Paton

发明人： Jeff Erhardt ,  Eric Paton

IPC分类号： H01L21285

CPC分类号： H01L29/66507 ,  H01L29/4933

摘要： The present invention relates to a method of forming a self-aligned silicide (salicide) by siliciding a gate area prior to siliciding a source and drain area and/or spacer formation. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area that is advantageously thicker than silicide formations over the source and drain areas.

摘要翻译： 本发明涉及通过在将源极和漏极区域和/或间隔物形成硅化之前将栅极区域硅化来形成自对准硅化物（自对准硅化物）的方法。 该方法通过降低源极和漏极区域中的漏电流并降低栅极的多晶硅片电阻来提高晶体管的速度。 作为本方法的一个实施例的结果，在栅极区域上形成硅化物，其优选在源极和漏极区域上比硅化物层更厚。