公开(公告)号：US5651127A

公开(公告)日：1997-07-22

申请号：US209123

申请日：1994-03-08

申请人： Robert J. Gove ,  Karl M. Guttag ,  Keith Balmer ,  Christopher J. Read ,  Iain Robertson ,  Nicholas Ing Simmons

发明人： Robert J. Gove ,  Karl M. Guttag ,  Keith Balmer ,  Christopher J. Read ,  Iain Robertson ,  Nicholas Ing Simmons

IPC分类号： G06F9/345 ,  G06F9/38 ,  G06F13/28 ,  G09G5/393 ,  G06F91/26 ,  G06F9/34 ,  G06F12/00 ,  G06F12/14

CPC分类号： G09G5/393 ,  G06F13/28 ,  G06F9/345 ,  G06F9/3879

摘要： This invention is a manner of control of the addresses of memory accesses. The data processing device of this invention includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, a number of guide table entries and a table pointer. The guide table includes guide table entries, each guide table entry having an address value and dimension values defining a block of addresses. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table. The address generating circuit may optionally form the predetermined combination of starting address and address value of guide table entry by adding the address value to the prior block starting address or by adding the guide table value to the starting address. The memory access may be a memory read from the block of addresses or a memory write to the block of addresses. In the preferred embodiment, memory, a data processor and a data transfer controller performing the above memory accesses is constructed in a single semiconductor chip. The data transfer controller may access external memory in the same manner as on-chip memory.

摘要翻译： 本发明是对存储器存取地址的控制方式。 本发明的数据处理装置包括存储器，控制电路，引导表和地址产生电路。 控制电路接收分组传送请求和分组传送参数。 分组传送参数包括起始地址，指导表条目的数目和表指针。 指南表包括指南表条目，每个指南表条目具有定义地址块的地址值和维度值。 表指针最初指向指南表中的第一个指南表项。 地址生成电路形成与每个引导表条目相对应的用于存储器访问的地址块集合，具有来自引导表条目的起始地址和地址值的预定组合的起始地址。 地址块由维度值形成。 在存储器访问之后，地址产生电路更新表指针以指向指南表中的下一条目。 地址产生电路可以通过将地址值添加到先前块开始地址或通过将引导表值添加到起始地址来可选地形成指南表入口的起始地址和地址值的预定组合。 存储器访问可以是从地址块读取的存储器或写入地址块的存储器。 在优选实施例中，执行上述存储器访问的存储器，数据处理器和数据传输控制器被构造在单个半导体芯片中。 数据传输控制器可以以与片上存储器相同的方式访问外部存储器。

公开(公告)号：US5524265A

公开(公告)日：1996-06-04

申请号：US207503

申请日：1994-03-08

申请人： Keith Balmer ,  Robert J. Gove ,  Iain Robertson ,  Karl M. Guttag ,  Nicholas Ing-Simmons

发明人： Keith Balmer ,  Robert J. Gove ,  Iain Robertson ,  Karl M. Guttag ,  Nicholas Ing-Simmons

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： This invention is a data processor including a data transfer controller. The data transfer controller includes internal and external memory interfaces coupled to internal and external memory, respectively. A pipeline controller controls the internal memory interface and the external memory interface. A source address generator generates addresses for reading data. A destination address generator generates addresses for writing data. Buffer circuitry interposed between the source address generator and the destination address generator permits data to be aligned to differing source and destination data word sizes and differing data word boundaries. An external sequencer provides control signals for the external memory via the external memory interface. In the preferred embodiment, the buffer circuitry includes a first-in-first-out (FIFO) buffer having a plurality of registers. This permits continued operations in many cases when either the source or destination memory operations temporarily stall. The buffer circuitry preferably is used for buffering processor requested data transfers. Also a further cache buffer having a plurality of registers is used in buffering instruction cache service requests. The data transfer controller includes refresh registers coupled to the external sequencer. This provides data refreshing of dynamic random access memories. The data transfer controller further includes request prioritization circuitry coupled to the pipeline controller for prioritization of data transfer requests to the pipeline controller.

摘要翻译： 本发明是一种包括数据传输控制器的数据处理器。 数据传输控制器分别包括耦合到内部和外部存储器的内部和外部存储器接口。 管道控制器控制内部存储器接口和外部存储器接口。 源地址生成器生成用于读取数据的地址。 目的地址生成器生成写入数据的地址。 插入在源地址发生器和目的地地址发生器之间的缓冲电路允许数据与不同的源和目的数据字大小和不同的数据字边界对准。 外部定序器通过外部存储器接口为外部存储器提供控制信号。 在优选实施例中，缓冲电路包括具有多个寄存器的先进先出（FIFO）缓冲器。 在许多情况下，当源或目标存储器操作暂时停止时，这允许持续的操作。 缓冲电路优选地用于缓冲处理器所请求的数据传输。 另外，在缓存指令高速缓存服务请求中使用具有多个寄存器的另外的高速缓存缓冲器。 数据传输控制器包括耦合到外部定序器的刷新寄存器。 这提供了动态随机存取存储器的数据刷新。 数据传输控制器还包括耦合到流水线控制器的请求优先化电路，用于将流量控制器的数据传输请求优先化。

公开(公告)号：US5724599A

公开(公告)日：1998-03-03

申请号：US208171

申请日：1994-03-08

申请人： Keith Balmer ,  Karl M. Guttag ,  Robert J. Gove ,  Nicholas Ing-Simmons ,  Iain Robertson

发明人： Keith Balmer ,  Karl M. Guttag ,  Robert J. Gove ,  Nicholas Ing-Simmons ,  Iain Robertson

IPC分类号： G06F15/00 ,  G06F15/16

CPC分类号： G06F15/16

摘要： The invention involves communication within a multiprocessor system. The multiprocessor system includes a command word bus and a plurality of data processors. Each data processor is connected to the command word bus and includes a command circuit, a decoder and a reset control circuit. The command circuit may generate a command word on the command word bus including at least one reset command word for resetting a data processor. The decoder decodes command words received via the command word bus and includes at least a reset command decoder for decoding a reset command word. The reset control circuit resets the data processor into a state corresponding to initial application of electrical power upon receiving a reset command word. Each command word circuit generates command words indicating a particular data processor to which it is directed. Only a predetermined subset of the data processors may send the reset command word directed to other data processors. Additional actions such as interrupts, halt and cache memory flush may be controlled via the command word. In the preferred embodiment, a single command word may be directed to plural data processors. In the preferred embodiment, the command word bus and each of the data processors are disposed on a single semiconductor chip.

摘要翻译： 本发明涉及多处理器系统内的通信。 多处理器系统包括命令字总线和多个数据处理器。 每个数据处理器连接到命令字总线，并包括命令电路，解码器和复位控制电路。 命令电路可以在命令字总线上生成包括用于复位数据处理器的至少一个复位命令字的命令字。 解码器解码通过命令字总线接收的命令字，并且至少包括用于对复位命令字进行解码的复位命令解码器。 复位控制电路在接收到复位命令字时将数据处理器复位为与初始施加电力相对应的状态。 每个命令字电路产生指示其所针对的特定数据处理器的命令字。 只有数据处理器的预定子集可以发送定向到其他数据处理器的复位命令字。 可以通过命令字来控制诸如中断，停止和高速缓冲存储器刷新等附加动作。 在优选实施例中，单个命令字可以被引导到多个数据处理器。 在优选实施例中，命令字总线和每个数据处理器设置在单个半导体芯片上。

公开(公告)号：US06314047B1

公开(公告)日：2001-11-06

申请号：US09713560

申请日：2000-11-15

申请人： John Keay ,  Iain Robertson ,  Karl M. Guttag ,  Keith Balmer

发明人： John Keay ,  Iain Robertson ,  Karl M. Guttag ,  Keith Balmer

IPC分类号： G11C800

CPC分类号： G11C11/412 ,  G11C8/16

摘要： Data transfer between multiple processor nodes and multiple static memory storage nodes is made more efficient using a wrapper of logic surrounding a conventional single port static memory function. The wrapper logic comprises FIFO devices which provide buffering between a given processor node and its associated memory function. The added buffering allows the design to trade allowable added read and write latency for a significant reduction in memory complexity. A single port random access memory structure enclosed within the wrapper provides the functional throughput advantage that only a dual port memory device would otherwise make possible.

摘要翻译： 使用围绕常规单端口静态存储器功能的逻辑封装件，使多个处理器节点和多个静态存储器存储节点之间的数据传输变得更有效。 封装逻辑包括提供给定处理器节点与其相关联的存储器功能之间的缓冲的FIFO设备。 添加的缓冲允许设计交易允许的增加的读和写延迟，显着降低内存复杂性。 包装在封装件中的单端口随机存取存储器结构提供了功能吞吐量优点，即只有双端口存储器件将成为可能。

公开(公告)号：US5956744A

公开(公告)日：1999-09-21

申请号：US706618

申请日：1996-09-06

申请人： Iain Robertson ,  Karl M. Guttag ,  Eric R. Hansen

发明人： Iain Robertson ,  Karl M. Guttag ,  Eric R. Hansen

IPC分类号： G06F12/12

CPC分类号： G06F12/123

摘要： A multilevel hierarchical least recently used cache replacement priority in a digital data processing system including plural memories, each memory connected to said system bus for memory access, a memory address generator generating addresses for read access to a corresponding of the memories and a memory cache having a plurality of cache entries, each cache entry including a range of addresses and a predetermined set of cache words. During each memory read the comparator compares the generated address with the address range of each cache entry. If there is a match, then the cache supplies a cache word corresponding to the least significant bits of the generated address from the matching cache entry. If there is no such match, the generated address is supplied to the memories and a set of words is recalled corresponding to the generated address. This set of words replaces a least recently used prior stored memory cache entry having the lowest priority level. The priority level for each cache entry may be recalled from a cache priority level look-up table or entered from an instruction via coding in opcode bits or a priority setting instruction. In an alternative embodiment this technique is used with a memory configuration cache storing memory access parameters for corresponding address ranges enabling adaption to plural memories requiring differing sets of memory access parameters.

摘要翻译： 在包括多个存储器的数字数据处理系统中的多级分级最低最近使用的高速缓存替换优先级，连接到所述系统总线的每个存储器用于存储器访问，存储器地址生成器产生用于对对应的存储器进行读访问的地址和具有 多个高速缓存条目，每个高速缓存条目包括地址范围和预定的一组高速缓存字。 在每个存储器读取期间，比较器将生成的地址与每个高速缓存条目的地址范围进行比较。 如果存在匹配，则高速缓存从匹配的高速缓存条目提供对应于生成的地址的最低有效位的缓存字。 如果没有这样的匹配，则将生成的地址提供给存储器，并且根据生成的地址来调用一组字。 这组文字替代了具有最低优先级的最近最少使用的先前存储的存储器高速缓存条目。 每个高速缓存条目的优先级可以从高速缓存优先级查找表调用，或者通过操作码中的编码或优先级设置指令从指令中输入。 在替代实施例中，该技术与存储器配置高速缓存一起使用，存储器访问参数用于相应的地址范围，使得能够适应需要不同组的存储器访问参数的多个存储器。

公开(公告)号：US07047284B1

公开(公告)日：2006-05-16

申请号：US09713440

申请日：2000-11-15

申请人： Sanjive Agarwala ,  David A. Comisky ,  Charles L. Fuoco ,  Iain Robertson ,  David Hoyle ,  John Keay ,  Keith Balmer ,  Amarjit S. Bhandal ,  Christopher L. Mobley

发明人： Sanjive Agarwala ,  David A. Comisky ,  Charles L. Fuoco ,  Iain Robertson ,  David Hoyle ,  John Keay ,  Keith Balmer ,  Amarjit S. Bhandal ,  Christopher L. Mobley

IPC分类号： G06F15/177

CPC分类号： G06F13/37

摘要： A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.

摘要翻译： 描述了转移请求总线和传送请求总线节点，其适用于处理多个并发转移请求的数据传输控制器，尽管在发生冲突的转移请求时产生了伴随的冲突。 传输请求从上游传输请求节点传递到下游传输请求节点，然后传送到具有队列的传输请求控制器。 在每个节点处，也可以插入本地传输请求以传递到传输控制器队列。 使用令牌传递方案来解决每个传送请求节点处的冲突，其中拥有令牌的传送请求节点允许优先于上游请求插入本地请求。

公开(公告)号：US06839831B2

公开(公告)日：2005-01-04

申请号：US09733597

申请日：2000-12-08

申请人： Keith Balmer ,  Richard D. Simpson ,  Iain Robertson ,  John Keay

发明人： Keith Balmer ,  Richard D. Simpson ,  Iain Robertson ,  John Keay

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/355 ,  G06F9/38 ,  G06F9/28

CPC分类号： G06F9/3885 ,  G06F9/3001 ,  G06F9/3012 ,  G06F9/355 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3891

摘要： A data processing apparatus includes first (78) and second (80) functional unit groups, each includes a plurality of functional units and a register file (76) comprising a plurality of registers. A comparator (181) receives the operand register number of a current instruction for a functional unit in the first functional unit group, and the destination register number of an immediately preceding instruction for the second functional unit group. A register file bypass multiplexer (174) selects the data from the register corresponding to the operand number of the current instruction on no match and selects the output of the second functional unit group (hotpath 172) if the comparator indicates a match. The first functional unit utilizes the output of the second functional unit group without waiting for the result to be stored in the register file.

摘要翻译： 数据处理装置包括第一（78）和第二（80）个功能单元组，每个功能单元组包括多个功能单元和包括多个寄存器的寄存器文件（76）。 比较器（181）接收第一功能单元组中的功能单元的当前指令的操作数寄存器号和第二功能单元组的紧接在前的指令的目的地寄存器号。 寄存器文件旁路多路复用器（174）在不匹配的情况下从当前指令的操作数编号对应的寄存器中选择数据，如果比较器指示匹配，则选择第二功能单元组（热路径172）的输出。 第一功能单元利用第二功能单元组的输出，而不等待结果存储在寄存器文件中。

公开(公告)号：US06654834B1

公开(公告)日：2003-11-25

申请号：US09615645

申请日：2000-07-13

申请人： Iain Robertson ,  John Keay ,  Amarjit S. Bhandal ,  Keith Balmer

发明人： Iain Robertson ,  John Keay ,  Amarjit S. Bhandal ,  Keith Balmer

IPC分类号： G06F100

CPC分类号： G06F15/173

摘要： Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus interface (311-318) which passes command, write data, address and read data to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data. This configuration retains the issued read and write order preserving proper function for read/write and write/read command pairs. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.

摘要翻译： 主节点（300）和多个存储节点（301-308）之间的数据传输遵循同步固定等待时间环路总线（255）。 每个存储器节点包括总线接口（311-318），其将命令，写入数据，地址和读取数据传递给循环中的下一个存储器节点。 如果读取命令被指向，则每个存储器节点在指定的地址处从其存储器执行读取。 如果写入命令被指向，则每个存储器节点对指定地址的存储器执行写操作。 无论访问哪个存储器节点，此配置都会在发出读命令和读取数据的返回之间提供固定的等待时间。 该配置可以防止返回的读取数据发生冲突。 该配置保留发出的读写顺序保持读/写和写/读命令对的正确功能。 该配置为每个阶段提供固定加载，而不管存储器节点的数量。 因此，简化了以高速运行的大型系统的设计。

公开(公告)号：US06185629B2

公开(公告)日：2001-02-06

申请号：US08208517

申请日：1994-03-08

申请人： Richard Simpson ,  Keith Balmer ,  Iain Robertson

发明人： Richard Simpson ,  Keith Balmer ,  Iain Robertson

IPC分类号： G06F1202

CPC分类号： G06F12/0215

摘要： This invention is a data processing apparatus which may interface with plural types of memories. A static decoder coupled to an external port decodes signals which from an external source that indicate the type of memory. Interface circuitry receives coded information from the static decoder and selects a protocol for information transfer. In the preferred embodiment, the protocol includes addressing information having multiplexed row/column addresses for accessing dynamic memories or un-multiplexed addresses for accessing static memories. The interface circuitry further includes a column address shifter. The column address shifter shifts address bits to vary the number of bits available for column addressing. The data processing apparatus attempts to use page mode addressing whenever possible. A lastpage register coupled to the address generator for stores previous address information. A comparator compares the previous address information stored in the lastpage register to the current address. If no page change is detected, the data processor supplies only the column address to the memory in a page mode cycle, or else the data processor supplies a full new address including both the row address and the column address. The data processing apparatus may also control the number of bits transferred. An external port supplies a bus size signal to a static decoder. The interface circuitry selects a a bus size protocol based upon the received bus size signal.

摘要翻译： 本发明是可以与多种类型的存储器接口的数据处理装置。 耦合到外部端口的静态解码器解码来自指示存储器类型的外部源的信号。 接口电路从静态解码器接收编码信息，并选择信息传输协议。 在优选实施例中，该协议包括具有用于访问动态存储器的复用行/列地址的寻址信息或用于访问静态存储器的未复用地址。 接口电路还包括列地址移位器。 列地址移位器移位地址位以改变列寻址可用的位数。 数据处理设备尽可能尝试使用页面模式寻址。 耦合到地址发生器的最后页寄存器用于存储先前的地址信息。 比较器将存储在最后页寄存器中的先前地址信息与当前地址进行比较。 如果没有检测到页面更改，则数据处理器在页面模式循环中仅向列表地址提供存储器，否则数据处理器将提供包含行地址和列地址的全新地址。 数据处理装置还可以控制传送的比特数。 外部端口向总线信号提供静态解码器。 接口电路基于所接收的总线大小信号来选择总线大小协议。

公开(公告)号：US20060236395A1

公开(公告)日：2006-10-19

申请号：US11241728

申请日：2005-09-30

申请人： David Barker ,  Clive Beavis ,  Robert Alasdair Bruce ,  Joan Garrett ,  Joshua Lubliner ,  Iain Robertson ,  Robert Ciccone ,  Prasad Akella

发明人： David Barker ,  Clive Beavis ,  Robert Alasdair Bruce ,  Joan Garrett ,  Joshua Lubliner ,  Iain Robertson ,  Robert Ciccone ,  Prasad Akella

IPC分类号： G06F12/14

CPC分类号： H04L63/1416 ,  G06F21/552 ,  H04L2463/102

摘要： A method is provided for conducting surveillance on a network. Data is captured on a network for a plurality of aggregated channels. The data is from individuals with network access identifiers that permit the individuals to gain access to the network, or applications on the network. The data is used to construct a plurality of session data streams. The session data streams provide a reconstruction of business activity participated in by the application or the individual with the network. A window of data is read in at least one of the plurality of session data streams to determine deviations. The window of data is tested against at least one filter. The at least one filter detects behavioral changes in the applications or the individuals that have the network access identifiers to access to the network. Defined intervention are taken in response to the deviations.

摘要翻译： 提供了一种用于在网络上进行监视的方法。 数据在网络上被捕获用于多个聚合信道。 数据来自具有允许个人访问网络或网络上的应用的具有网络访问标识符的个人。 该数据用于构建多个会话数据流。 会话数据流提供由应用程序或个人与网络参与的业务活动的重建。 在多个会话数据流中的至少一个中读取数据窗口以确定偏差。 根据至少一个过滤器测试数据窗口。 所述至少一个过滤器检测应用程序或具有访问网络的网络访问标识符的个人的行为变化。 定义的干预是针对偏差进行的。