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1.发明申请公开(公告)号：US20070064699A1
公开(公告)日：2007-03-22
申请号：US11229109
申请日：2005-09-16
IPC分类号： H04L12/28
CPC分类号： H04L45/34 , H04L45/02 , H04L45/24 , H04L45/72 , H04L47/50 , H04L47/56 , H04L47/562 , H04L47/568 , H04L47/623 , H04L47/6255
摘要： Techniques for routing data packets in a networked system. Specifically, a network system and methods of arbitrating data packets in a network system are provided. Switching devices are configured to receive one or more data packets, wherein each of the one or more data packets includes a respective source identification. The source identifications are compared to a source identification history mechanism, and the routing order of the data packets is determined based on the comparison.
摘要翻译： 在网络系统中路由数据包的技术。 具体地说，提供网络系统和网络系统中的数据分组仲裁方法。 交换设备被配置为接收一个或多个数据分组，其中所述一个或多个数据分组中的每一个包括相应的源标识。 将源标识与源识别历史机制进行比较，并且基于比较确定数据分组的路由顺序。
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2.发明申请Method and system of copying a memory area between processor elements for lock-step execution 有权在处理器元件之间复制存储区域以进行锁步执行的方法和系统公开(公告)号：US20060242461A1
公开(公告)日：2006-10-26
申请号：US11114318
申请日：2005-04-26
申请人： Thomas Kondo , Robert Jardine , James Klecka , William Brunckert , David Garcia , James Smullen , Patrick Barnes
发明人： Thomas Kondo , Robert Jardine , James Klecka , William Brunckert , David Garcia , James Smullen , Patrick Barnes
IPC分类号： G06F11/00
CPC分类号： G06F11/1658 , G06F9/3824 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F11/1683 , G06F11/1687 , G06F11/185
摘要： A method and system of copying a memory area between processor elements for lock-step execution. At least some of the illustrative embodiments may be a method comprising executing duplicate copies of a first program in a first processor of a first multiprocessor computer system and in a first processor of a second multiprocessor computer system (the executing substantially in lock-step), executing a second program in a second processor element of the first multiprocessor computer system (the first and second processors of the first multiprocessor computer system sharing an input/output (I/O) bridge), copying a memory area of the second program executing in the second processor element of the first multiprocessor computer system to a memory of a second processor element in the second multiprocessor computer system while the duplicate copies of the first program are executing in the first processor elements, and then executing duplicate copies of the second program in the second processors in lock-step.
摘要翻译： 在处理器元件之间复制存储区域以进行锁步执行的方法和系统。 示例性实施例中的至少一些可以是包括在第一多处理器计算机系统的第一处理器和第二多处理器计算机系统的第一处理器中执行第一程序的重复副本（执行基本上是锁定步骤）的方法， 在第一多处理器计算机系统的第二处理器元件（共享输入/输出（I / O）桥的第一多处理器计算机系统的第一和第二处理器）中执行第二程序，复制第二程序中执行的第二程序的存储区域 所述第一多处理器计算机系统的第二处理器元件到所述第二多处理器计算机系统中的第二处理器元件的存储器，同时所述第一程序的副本在所述第一处理器元件中执行，然后执行所述第二程序的副本 第二个处理器在锁步。
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公开(公告)号：US20050223275A1
公开(公告)日：2005-10-06
申请号：US11071944
申请日：2005-03-04
申请人： Robert Jardine , James Smullen , Graham Stott , John Friedenbach
发明人： Robert Jardine , James Smullen , Graham Stott , John Friedenbach
CPC分类号： G06F11/1658 , G06F9/52 , G06F11/1641 , G06F11/1645 , G06F11/165 , G06F11/1683 , G06F11/1687 , G06F11/184 , G06F11/185 , G06F11/3404 , G06F11/3476 , G06F11/3495 , G06F11/3636 , G06F11/366 , G06F2201/88
摘要： Performance data access is described. In an embodiment, events are processed with non-synchronized processor elements of a logical processor in a redundant processor system. Performance data associated with execution of the processor events is stored in one or more accumulators corresponding to a respective processor element. The performance data from each of the non-synchronized processor elements is exchanged via a logical synchronization unit such that each processor element includes the performance data from each of the processor elements. Each processor element then conforms the performance data to generate synchronized performance data which is then communicated to a performance monitoring application that requests the performance data from the logical processor.
摘要翻译： 描述性能数据访问。 在一个实施例中，事件在冗余处理器系统中用逻辑处理器的非同步处理器元件处理。 与执行处理器事件相关联的性能数据被存储在对应于相应处理器元件的一个或多个累加器中。 来自每个非同步处理器元件的性能数据经由逻辑同步单元交换，使得每个处理器元件包括来自每个处理器元件的性能数据。 然后，每个处理器元件符合性能数据以产生同步的性能数据，然后将其传送到从逻辑处理器请求性能数据的性能监视应用程序。
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公开(公告)号：US20060031702A1
公开(公告)日：2006-02-09
申请号：US10894784
申请日：2004-07-20
申请人： Robert Jardine , Russell Rector
发明人： Robert Jardine , Russell Rector
CPC分类号： G06F1/14
摘要： In an implementation of time of day response, time logic executed by each processor element of a logical processor generates a logical time in response to a time of day request. The logical time is generated to approximate the actual time such that each processor element of the logical processor returns the same logical time.
摘要翻译： 在时间响应的实现中，由逻辑处理器的每个处理器元件执行的时间逻辑响应于时间请求而产生逻辑时间。 生成逻辑时间以近似实际时间，使得逻辑处理器的每个处理器元件返回相同的逻辑时间。
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公开(公告)号：US1120441A
公开(公告)日：1914-12-08
申请号：US1914853229
申请日：1914-07-25
申请人： ROBERT JARDINE , BROWN JOHN ROBERT
发明人： BROWN JOHN ROBERT
CPC分类号： F23C99/00
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6.发明申请Software transparent expansion of the number of fabrics coupling multiple processsing nodes of a computer system 审中-公开软件透明扩展耦合计算机系统的多个处理节点的结构数量公开(公告)号：US20060031622A1
公开(公告)日：2006-02-09
申请号：US11048525
申请日：2005-02-01
申请人： Robert Jardine
发明人： Robert Jardine
IPC分类号： G06F13/36
摘要： The number of fabrics coupling a plurality of processing nodes of a computer system is expanded from a first fabric and second fabric known to the I/O services layer residing at each processing nodes to a first and second plurality of fabrics. A current mapping is maintained at each of the processing nodes between the first fabric and one of the first plurality of fabrics and between the second fabric and one of the second plurality of fabrics for each of the processing nodes. Messages are transmitted by one or of the plurality of processing nodes acting as a source node to one or more of the other processing nodes as a destination node over one of the first and second plurality of fabrics in accordance with the current mapping for the destination node residing at the source node and based on which of the first and second fabrics are specified in the requests of the I/O services layers.
摘要翻译： 耦合计算机系统的多个处理节点的织物的数量从驻留在每个处理节点处的I / O服务层已知的第一和第二织物扩展到第一和第二多个织物。 在第一结构和第一多个结构之一之间以及处理节点之间的第二个结构和第二个多个结构之一之间的每个处理节点之间维护当前映射。 根据目的地节点的当前映射，消息由用作源节点的一个或多个处理节点发送到作为第一和第二多个结构之一的其他处理节点中的一个或多个作为目的地节点 驻留在源节点处，并且基于在I / O服务层的请求中指定第一和第二结构中的哪一个。
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公开(公告)号：US20060020850A1
公开(公告)日：2006-01-26
申请号：US10894825
申请日：2004-07-20
申请人： Robert Jardine , David Bernick , Thomas Heynemann , James Smullen
发明人： Robert Jardine , David Bernick , Thomas Heynemann , James Smullen
IPC分类号： G06F11/00
CPC分类号： G06F11/1666 , G06F11/1004 , G06F11/1633
摘要： In an implementation of latent error detection, memory regions that each correspond to a different processor element of a redundant processor system are scanned for latent processing errors maintained as erroneous data. The data maintained in the memory regions is compared to detect a latent processing error in a first memory region. The latent processing error is resolved by copying data from a second memory region into the first memory region where the data maintained in the second memory region is determined to be identical to data maintained in at least a third memory region.
摘要翻译： 在潜在错误检测的实现中，扫描每个对应于冗余处理器系统的不同处理器元件的存储器区域作为错误数据维护的潜在处理错误。 将保存在存储器区域中的数据进行比较，以检测第一存储器区域中的潜在处理误差。 通过将数据从第二存储器区域复制到第一存储器区域中来解决潜在处理错误，其中保持在第二存储器区域中的数据被确定为与至少第三存储器区域中保持的数据相同。
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8.发明申请Method and system of determining whether a user program has made a system level call 失效确定用户程序是否进行了系统级别调用的方法和系统公开(公告)号：US20050246587A1
公开(公告)日：2005-11-03
申请号：US11042981
申请日：2005-01-25
申请人： David Bernick , William Bruckert , David Garcia , Robert Jardine , Pankaj Mehra , James Smullen
发明人： David Bernick , William Bruckert , David Garcia , Robert Jardine , Pankaj Mehra , James Smullen
CPC分类号： G06F11/1658 , G06F9/52 , G06F11/1641 , G06F11/1645 , G06F11/165 , G06F11/1683 , G06F11/1687 , G06F11/184 , G06F11/185 , G06F11/3404 , G06F11/3476 , G06F11/3495 , G06F11/3636 , G06F11/366 , G06F2201/88
摘要： Method and system of determining whether a user program has made a system level call and thus whether the user program is uncooperative with fault tolerant operation. Some exemplary embodiments may be a processor-based method comprising providing information from a first processor to a second processor (the information indicating that a user program executed on the first processor has not made a system level call in a predetermined amount of time), and determining by the first processor, using information from the second processor, whether a duplicate copy of the user program substantially simultaneously executed in the second processor has made a system level call in the predetermined amount of time.
摘要翻译： 确定用户程序是否进行了系统级别的调用以及用户程序是否不兼容容错操作的方法和系统。 一些示例性实施例可以是基于处理器的方法，包括从第一处理器向第二处理器提供信息（指示在第一处理器上执行的用户程序在预定时间量内没有进行系统级别调用的信息），以及 由第一处理器确定使用来自第二处理器的信息，在第二处理器中基本上同时执行的用户程序的副本是否在预定的时间量内进行了系统级的调用。
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9.发明申请公开(公告)号：US20050223274A1
公开(公告)日：2005-10-06
申请号：US11042548
申请日：2005-01-25
申请人： David Bernick , William Bruckert , David Garcia , Robert Jardine , James Klecka , Pankaj Mehra , James Smullen
发明人： David Bernick , William Bruckert , David Garcia , Robert Jardine , James Klecka , Pankaj Mehra , James Smullen
CPC分类号： G06F11/1683 , G06F9/3851 , G06F9/3861 , G06F11/1482 , G06F11/1645 , G06F11/1691
摘要： A method and system of loosely lock-stepped non-deterministic processors. Some exemplary embodiments may be a processor-based method comprising executing fault tolerant copies of a user program, one copy of the user program executed in a first processor performing non-deterministic execution, and a duplicate copy of the user program executing in a second processor performing non-deterministic execution, with the executing in the first processor and second processor not in cycle-by-cycle lock-stepped.
摘要翻译： 松散锁定非确定性处理器的方法和系统。 一些示例性实施例可以是基于处理器的方法，包括执行用户程序的容错副本，在执行非确定性执行的第一处理器中执行的用户程序的一个副本以及在第二处理器中执行的用户程序的副本 执行非确定性执行，其中在第一处理器和第二处理器中的执行不是按循环逐步锁定。
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公开(公告)号：US20060242456A1
公开(公告)日：2006-10-26
申请号：US11114319
申请日：2005-04-26
申请人： Thomas Kondo , Robert Jardine , William Bruckert , David Garcia , James Klecka , James Smullen , Jeff Sprouse , Graham Stott
发明人： Thomas Kondo , Robert Jardine , William Bruckert , David Garcia , James Klecka , James Smullen , Jeff Sprouse , Graham Stott
IPC分类号： G06F11/00
CPC分类号： G06F11/1658
摘要： A method and system of copying memory from a source processor to a target processor by duplicating memory writes. At least some of the exemplary embodiments may be a method comprising stopping execution of a user program on a target processor (the target processor coupled to a first memory), continuing to execute a duplicate copy of the user program on a source processor (the source processor coupled to a second memory and generating writes to the second memory), duplicating memory writes of the source processor and duplicating writes by input/output adapters to create a stream of duplicate memory writes, and applying the duplicated memory writes to the first memory.
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