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公开(公告)号：US20110010501A1
公开(公告)日：2011-01-13
申请号：US12763938
申请日：2010-04-20
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A BIU prioritizes L1 requests above L2 requests. The L2 generates a first request to the BIU and detects the generation of a snoop request and L1 request to the same cache line. The L2 determines whether a bus transaction to fulfill the first request may be retried and, if so, generates a miss, and otherwise generates a hit. Alternatively, the L2 detects the L1 generated a request to the L2 for the same line and responsively requests the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted the bus. Alternatively, a prefetch cache and the L2 allow the same line to be simultaneously present. If an L1 request hits in both the L2 and in the prefetch cache, the prefetch cache invalidates its copy of the line and the L2 provides the line to the L1.
摘要翻译： BIU将L1请求优先于L2请求。 L2产生对BIU的第一个请求，并检测到窥探请求和L1请求到同一个高速缓存行的生成。 L2确定是否可以重试履行第一请求的总线事务，如果是，则产生未命中，否则生成命中。 或者，L2检测到L1产生对同一行的L2的请求，并且如果BIU尚未被授予总线，则响应地请求BIU在总线上不执行交易以执行第一请求。 或者，预取高速缓存和L2允许同时存在同一行。 如果L1请求都在L2和预取缓存中同时进行，则预取缓存使其副本无效，并且L2向L1提供该行。
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公开(公告)号：US20120272003A1
公开(公告)日：2012-10-25
申请号：US13535152
申请日：2012-06-27
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A microprocessor configured to access an external memory includes a first-level cache, a second-level cache, and a bus interface unit (BIU) configured to interface the first-level and second-level caches to a bus used to access the external memory. The BIU is configured to prioritize requests from the first-level cache above requests from the second-level cache. The second-level cache is configured to generate a first request to the BIU to fetch a cache line from the external memory. The second-level cache is also configured to detect that the first-level cache has subsequently generated a second request to the second-level cache for the same cache line. The second-level cache is also configured to request the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted ownership of the bus to fulfill the first request.
摘要翻译： 被配置为访问外部存储器的微处理器包括：第一级高速缓存，第二级高速缓存和总线接口单元（BIU），其被配置为将第一级和第二级高速缓存连接到用于访问外部存储器的总线 。 BIU被配置为优先考虑来自第二级缓存的来自第二级缓存的请求的请求。 第二级缓存被配置为生成对BIU的第一请求以从外部存储器获取高速缓存行。 第二级缓存还被配置为检测第一级高速缓存随后已经为同一高速缓存行生成了第二级缓存的第二请求。 第二级缓存还被配置为如果BIU尚未被授予总线的所有权以满足第一请求，则要求BIU避免在总线上执行事务以满足第一请求。
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公开(公告)号：US20120272004A1
公开(公告)日：2012-10-25
申请号：US13535188
申请日：2012-06-27
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A memory subsystem in a microprocessor includes a first-level cache, a second-level cache, and a prefetch cache configured to speculatively prefetch cache lines from a memory external to the microprocessor. The second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both. If a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache.
摘要翻译： 微处理器中的存储器子系统包括第一级高速缓存，第二级高速缓存和预取高速缓存，其被配置为从微处理器外部的存储器推测性地预取高速缓存行。 二级缓存和预取缓存被配置为允许同一个高速缓存行同时存在于两者中。 如果缓存行的第一级缓存的请求在二级缓存和预取高速缓存中都击中，则预取缓存使其高速缓存行的副本无效，并且第二级缓存将高速缓存行提供给第一级高速缓存 级缓存。
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公开(公告)号：US08234450B2
公开(公告)日：2012-07-31
申请号：US12763938
申请日：2010-04-20
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A BIU prioritizes L1 requests above L2 requests. The L2 generates a first request to the BIU and detects the generation of a snoop request and L1 request to the same cache line. The L2 determines whether a bus transaction to fulfill the first request may be retried and, if so, generates a miss, and otherwise generates a hit. Alternatively, the L2 detects the L1 generated a request to the L2 for the same line and responsively requests the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted the bus. Alternatively, a prefetch cache and the L2 allow the same line to be simultaneously present. If an L1 request hits in both the L2 and in the prefetch cache, the prefetch cache invalidates its copy of the line and the L2 provides the line to the L1.
摘要翻译： BIU将L1请求优先于L2请求。 L2产生对BIU的第一个请求，并检测到窥探请求和L1请求到同一个高速缓存行的生成。 L2确定是否可以重试履行第一请求的总线事务，如果是，则产生未命中，否则生成命中。 或者，L2检测到L1产生对同一行的L2的请求，并且如果BIU尚未被授予总线，则响应地请求BIU在总线上不执行交易以执行第一请求。 或者，预取高速缓存和L2允许同时存在同一行。 如果L1请求都在L2和预取缓存中同时进行，则预取缓存使其副本无效，并且L2向L1提供该行。
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公开(公告)号：US08543765B2
公开(公告)日：2013-09-24
申请号：US13535188
申请日：2012-06-27
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A memory subsystem in a microprocessor includes a first-level cache, a second-level cache, and a prefetch cache configured to speculatively prefetch cache lines from a memory external to the microprocessor. The second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both. If a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache.
摘要翻译： 微处理器中的存储器子系统包括第一级高速缓存，第二级高速缓存和预取高速缓存，其被配置为从微处理器外部的存储器推测性地预取高速缓存行。 二级缓存和预取缓存被配置为允许同一个高速缓存行同时存在于两者中。 如果缓存行的第一级缓存的请求在二级缓存和预取高速缓存中都击中，则预取缓存使其高速缓存行的副本无效，并且第二级缓存将高速缓存行提供给第一级高速缓存 级缓存。
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公开(公告)号：US08489823B2
公开(公告)日：2013-07-16
申请号：US13535152
申请日：2012-06-27
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0859 , G06F12/0897 , G06F2212/6022
摘要： A microprocessor configured to access an external memory includes a first-level cache, a second-level cache, and a bus interface unit (BIU) configured to interface the first-level and second-level caches to a bus used to access the external memory. The BIU is configured to prioritize requests from the first-level cache above requests from the second-level cache. The second-level cache is configured to generate a first request to the BIU to fetch a cache line from the external memory. The second-level cache is also configured to detect that the first-level cache has subsequently generated a second request to the second-level cache for the same cache line. The second-level cache is also configured to request the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted ownership of the bus to fulfill the first request.
摘要翻译： 被配置为访问外部存储器的微处理器包括：第一级高速缓存，第二级高速缓存和总线接口单元（BIU），其被配置为将第一级和第二级高速缓存连接到用于访问外部存储器的总线 。 BIU被配置为优先考虑来自第二级缓存的来自第二级缓存的请求的请求。 第二级缓存被配置为生成对BIU的第一请求以从外部存储器获取高速缓存行。 第二级缓存还被配置为检测第一级高速缓存随后已经为同一高速缓存行生成了第二级缓存的第二请求。 第二级缓存还被配置为如果BIU尚未被授予总线的所有权以满足第一请求，则要求BIU避免在总线上执行事务以满足第一请求。
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7.发明授权Apparatus and method for performing a detached load operation in a pipeline microprocessor 有权在管道微处理器中执行分离的负载操作的装置和方法公开(公告)号：US07191320B2
公开(公告)日：2007-03-13
申请号：US10776751
申请日：2004-02-11
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3861
摘要： A pipeline microprocessor that distributes the instruction dispatching function between a main instruction dispatcher and dispatching logic within a plurality of execution units is disclosed. If the main instruction dispatcher requests load data from a data cache that indicates the data is unavailable, the instruction dispatcher provides to the appropriate execution unit the load instruction (without the load data), a tag (also known by the cache) uniquely identifying the unavailable data, and a false data valid indicator. The cache subsequently obtains the data and outputs it on a bus along with the tag. The dispatching logic in the execution unit is monitoring the bus looking for a valid tag that matches tags of entries in its queue with invalid data indicators. Upon a match, the dispatching logic obtains the data from the bus and subsequently dispatches the instruction along with the data to a functional unit for execution.
摘要翻译： 公开了一种在主指令分派器和多个执行单元内的调度逻辑之间分配指令调度功能的流水线微处理器。 如果主指令分派器请求从指示数据不可用的数据高速缓存中加载数据，则指令分派器向合适的执行单元提供加载指令（无加载数据），唯一标识 不可用数据，以及虚假数据有效指标。 缓存随后获得数据并将其与标签一起在总线上输出。 执行单元中的调度逻辑正在监视总线，寻找与无效数据指示符匹配其队列中条目的标签的有效标签。 在匹配时，调度逻辑从总线获得数据，随后将指令与数据一起发送到功能单元以供执行。
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8.发明授权Method and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state register 失效在利用机器状态寄存器内的特殊访问位的超标量处理器系统内选择性地支持非架构指令的方法和系统
公开(公告)号：US5758141A
公开(公告)日：1998-05-26
申请号：US386977
申请日：1995-02-10
CPC分类号： G06F9/30181 , G06F9/30145 , G06F9/30189 , G06F9/45554
摘要： A method and system for permitting the selective support of non-architected instructions within a superscalar processor system. A special access bit within the system machine state register is provided and set in response to each initiation of an application during which execution of non-architected instructions is desired. Thereafter, each time a non-architected instruction is decoded the status of the special access bit is determined. The non-architected instruction is executed in response to a set state of the special access bit. The illegal instruction program interrupt is issued in response to an attempted execution of a non-architected instruction if the special access bit is not set. In this manner, for example, complex instruction set computing (CISC) instructions may be selectively enabled for execution within a reduced instruction set computing (RISC) data processing system while maintaining full architectural compliance with the reduced instruction set computing (RISC) instructions.
摘要翻译： 一种用于允许在超标量处理器系统内选择性地支持非架构指令的方法和系统。 系统机器状态寄存器内的特殊访问位被提供和设置为响应于期望执行非架构指令的应用程序的每个启动。 此后，每当非架构化指令被解码时，确定特殊访问位的状态。 响应于特殊访问位的设置状态执行非架构指令。 如果未设置特殊访问位，则响应于非架构化指令的尝试执行而发出非法指令程序中断。 以这种方式，例如，复杂指令集计算（CISC）指令可以选择性地启用以在精简指令集计算（RISC）数据处理系统中执行，同时保持与精简指令集计算（RISC）指令的完全架构符合性。
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9.发明授权Method for executing speculative load instructions in high-performance processors 失效在高性能处理器中执行推测加载指令的方法
公开(公告)号：US5611063A
公开(公告)日：1997-03-11
申请号：US597647
申请日：1996-02-06
CPC分类号： G06F9/30043 , G06F9/383 , G06F9/3842
摘要： A method for selectively executing speculative load instructions in a high-performance processor is disclosed. In accordance with the present disclosure, when a speculative load instruction for which the data is not stored in a data cache is encountered, a bit within an enable speculative load table which is associated with that particular speculative load instruction is read in order to determine a state of the bit. If the associated bit is in a first state, data for the speculative load instruction is requested from a system bus and further execution of the speculative load instruction is then suspended to wait for control signals from a branch processing unit. If the associated bit is in a second state, the execution of the speculative load instruction is immediately suspended to wait for control signals from the branch processing unit. If the speculative load instruction is executed in response to the control signals, then the associated bit in the enable speculative load table will be set to the first state. However, if the speculative load instruction is not executed in response to the control signals, then the associated bit in the enable speculative load table is set to the second state. In this manner, the displacement of useful data in the data cache due to wrongful execution of the speculative load instruction is avoided.
摘要翻译： 公开了一种用于选择性地执行高性能处理器中的推测性加载指令的方法。 根据本公开，当遇到数据未被存储在数据高速缓冲存储器中的推测性加载指令时，读取与该特定推测加载指令相关联的使能投机载入表中的位，以便确定 状态的位。 如果关联位处于第一状态，则从系统总线请求用于推测加载指令的数据，然后暂停推测加载指令的进一步执行，以等待来自分支处理单元的控制信号。 如果相关联的位处于第二状态，则推测加载指令的执行被立即停止，以等待来自分支处理单元的控制信号。 如果响应于控制信号执行推测加载指令，则使能推测加载表中的关联位将被设置为第一状态。 然而，如果不响应于控制信号执行推测加载指令，则使能推测负载表中的关联位被设置为第二状态。 以这种方式，避免了由于推测加载指令的错误执行而在数据高速缓存中的有用数据的位移。
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10.发明授权公开(公告)号：US08051116B2
公开(公告)日：2011-11-01
申请号：US12037596
申请日：2008-02-26
IPC分类号： G06F7/00
CPC分类号： G06F9/3001 , G06F9/30036
摘要： A method for executing an MMX PSADBW instruction by a microprocessor. The method includes generating packed differences of packed operands of the instruction and generating borrow bits associated with each of the packed differences; for each of the packed differences: determining whether the borrow bit indicates the packed difference is positive or negative and selecting a value in response to the determining, the value comprising the packed difference if the associated borrow bit is positive and a complement of the packed difference if the associated borrow bit is negative; adding the selected values to generate a first sum and a first carry and in parallel adding the borrow bits to generate a second sum and a second carry; adding the first and second sums and the first and second carries to generate a result of the instruction; storing the result in a register of the microprocessor.
摘要翻译： 一种用于由微处理器执行MMX PSADBW指令的方法。 该方法包括生成指令的打包操作数的压缩差，并产生与每个压缩差相关联的借位; 对于每个压缩差异：确定借位位是否指示压缩差是正还是负，并且响应于确定选择值，如果相关联的借位位为正，则包含压缩差的值，以及压缩差的补数 如果相关的借位是负数; 添加所选择的值以产生第一和和第一进位并且并行地加上借位位以产生第二和和第二进位; 添加第一和第二和和第一和第二输入以产生指令的结果; 将结果存储在微处理器的寄存器中。
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