公开(公告)号：US20150102413A1

公开(公告)日：2015-04-16

申请号：US14505788

申请日：2014-10-03

Applicant: Raheel AZMAT ,  RWIK SENGUPTA ,  CHULHONG PARK ,  KWANYOUNG CHUN

Inventor： Raheel AZMAT ,  RWIK SENGUPTA ,  CHULHONG PARK ,  KWANYOUNG CHUN

IPC: H01L27/24 ,  H01L23/538

CPC classification number: H01L27/11807 ,  H01L23/535 ,  H01L23/5384 ,  H01L27/0207 ,  H01L29/0649 ,  H01L2924/0002 ,  H03K19/1736 ,  H01L2924/00

Abstract: Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction.

Abstract translation: 提供了一种半导体器件，其包括具有多个逻辑单元的衬底，设置在多个逻辑单元中的晶体管，连接到晶体管的电极的接触插塞，与接触插塞的顶表面接触的第一通孔插头， 与第一通孔插头的顶表面接触。 第一导线可以包括通过接触插头连接到多个逻辑单元的公共导线，并且所有第一导线可以形状为平行于特定方向延伸的直线。

公开(公告)号：US20160111421A1

公开(公告)日：2016-04-21

申请号：US14828509

申请日：2015-08-17

Applicant: Mark S. RODDER ,  Rwik SENGUPTA ,  Borna OBRADOVIC

Inventor： Mark S. RODDER ,  Rwik SENGUPTA ,  Borna OBRADOVIC

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L27/0886 ,  H01L21/28123 ,  H01L21/823437 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: An integrated circuit comprises at least one block comprising a first cell and a second cell. The first cell comprises a first FET formed with a first contacted poly pitch (CPP), and the second cell comprises a second FET formed with a second CPP. The first CPP is greater than the second CPP. The first FET is part of a critical-speed path, and the second FET is part of a noncritical-speed path, in which the critical-speed path operates at a faster speed than the noncritical-speed path. The first FET and the second FET each comprise a planar FET, a finFET, a gate-all-around FET or a nanosheet FET. A method for forming the integrated circuit is also disclosed.

Abstract translation: 集成电路包括至少一个包括第一单元和第二单元的块。 第一单元包括形成有第一接触聚间距（CPP）的第一FET，并且第二单元包括由第二CPP形成的第二FET。 第一个CPP大于第二个CPP。 第一个FET是临界速度路径的一部分，第二个FET是非临界速度路径的一部分，其中临界速度路径以比非临界速度路径更快的速度运行。 第一FET和第二FET各自包括平面FET，finFET，栅极全环FET或纳米片FET。 还公开了一种用于形成集成电路的方法。

公开(公告)号：US20160104787A1

公开(公告)日：2016-04-14

申请号：US14878230

申请日：2015-10-08

Applicant: Jorge A. Kittl ,  Ganesh Hegde ,  Rwik Sengupta ,  Borna J. Obradovic ,  Mark S. Rodder

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Rwik Sengupta ,  Borna J. Obradovic ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L29/417

CPC classification number: H01L29/665 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76843 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming a plurality of fin-shaped channels on a substrate, forming a gate structure crossing over the plurality of fin-shaped channels and forming a source/drain adjacent a side of the gate structure. The source/drain may cross over the plurality of fin-shaped channels and may be electrically connected to the plurality of fin-shaped channels. The methods may also include forming a metallic layer on an upper surface of the source/drain and forming a conductive contact on the metallic layer opposite the source/drain. The conductive contact may have a first length in a longitudinal direction of the metallic layer that is less than a second length of the metallic layer in the longitudinal direction of the metallic layer.

Abstract translation: 提供了形成半导体器件的方法。 所述方法可以包括在衬底上形成多个鳍形通道，形成跨越多个鳍形通道的栅极结构，并且在栅极结构的一侧形成源极/漏极。 源极/漏极可以跨越多个鳍状沟道并且可以电连接到多个鳍状沟道。 所述方法还可以包括在源极/漏极的上表面上形成金属层，并在与源极/漏极相对的金属层上形成导电接触。 导电接触可以在金属层的纵向方向上具有小于金属层在金属层的纵向方向上的第二长度的第一长度。

公开(公告)号：US08963210B2

公开(公告)日：2015-02-24

申请号：US13238655

申请日：2011-09-21

Applicant: Rwik Sengupta ,  Rohit Kumar Gupta ,  Mitesh Goyal ,  Olivier Menut

Inventor： Rwik Sengupta ,  Rohit Kumar Gupta ,  Mitesh Goyal ,  Olivier Menut

IPC: H01L23/52 ,  H01L27/118 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/11807 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit (IC) cell may include first and second semiconductor regions, and parallel electrically conductive lines extending above the first and second semiconductor regions. The IC cell may further include electrically conductive line contacts electrically connected to the parallel electrically conductive lines, and may include at least one first line contact between the first semiconductor region and a corresponding end of the IC cell, and at least one second line contact between the first semiconductor region and the second semiconductor region. Adjacent ones of the electrically conductive lines may be respectively coupled to one of the at least one first line contact and to one of the at least one second line contact.

Abstract translation: 集成电路（IC）单元可以包括第一和第二半导体区域以及在第一和第二半导体区域上方延伸的平行导电线。 IC单元还可以包括电连接到并行导电线的导电线触点，并且可以包括在第一半导体区域和IC单元的对应端之间的至少一个第一线接触，以及至少一个第二线接触 第一半导体区域和第二半导体区域。 相邻的导电线可以分别耦合到至少一个第一线路触点中的一个和至少一个第二线路触点中的一个。

公开(公告)号：US20120132963A1

公开(公告)日：2012-05-31

申请号：US13238655

申请日：2011-09-21

Applicant: Rwik Sengupta ,  Rohit Kumar Gupta ,  Mitesh Goyal ,  Olivier Menut

Inventor： Rwik Sengupta ,  Rohit Kumar Gupta ,  Mitesh Goyal ,  Olivier Menut

IPC: H01L23/48 ,  H01L21/82

CPC classification number: H01L27/11807 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit (IC) cell may include first and second semiconductor regions, and parallel electrically conductive lines extending above the first and second semiconductor regions. The IC cell may further include electrically conductive line contacts electrically connected to the parallel electrically conductive lines, and may include at least one first line contact between the first semiconductor region and a corresponding end of the IC cell, and at least one second line contact between the first semiconductor region and the second semiconductor region. Adjacent ones of the electrically conductive lines may be respectively coupled to one of the at least one first line contact and to one of the at least one second line contact.

Abstract translation: 集成电路（IC）单元可以包括第一和第二半导体区域以及在第一和第二半导体区域上方延伸的平行导电线。 IC单元还可以包括电连接到并行导电线的导电线触点，并且可以包括在第一半导体区域和IC单元的对应端之间的至少一个第一线接触，以及至少一个第二线接触 第一半导体区域和第二半导体区域。 相邻的导电线可以分别耦合到至少一个第一线路触点中的一个和至少一个第二线路触点中的一个。

公开(公告)号：US10361195B2

公开(公告)日：2019-07-23

申请号：US14834419

申请日：2015-08-24

Applicant: Rwik Sengupta ,  Mark S. Rodder

Inventor： Rwik Sengupta ,  Mark S. Rodder

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/02

Abstract: An embodiment includes a semiconductor device, comprising: a substrate; a continuous diffusion region disposed on the substrate; a first gate structure disposed on the continuous diffusion region; a second gate structure disposed on the continuous diffusion region; an isolation gate structure disposed between the first gate structure and the second gate structure and disposed adjacent to the both the first gate structure and the second gate structure; a first diffusion region of the continuous diffusion region disposed between the first gate structure and the isolation gate structure; a second diffusion region of the continuous diffusion region disposed between the second gate structure and the isolation gate structure; a conductive layer disposed on the first and second diffusion regions; and an isolation gate contact disposed over the isolation gate structure and electrically insulated from the first diffusion region.

公开(公告)号：US10297673B2

公开(公告)日：2019-05-21

申请号：US14878230

申请日：2015-10-08

Applicant: Jorge A. Kittl ,  Ganesh Hegde ,  Rwik Sengupta ,  Borna J. Obradovic ,  Mark S. Rodder

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Rwik Sengupta ,  Borna J. Obradovic ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/285 ,  H01L23/485 ,  H01L29/78 ,  H01L29/165 ,  H01L21/768

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming a plurality of fin-shaped channels on a substrate, forming a gate structure crossing over the plurality of fin-shaped channels and forming a source/drain adjacent a side of the gate structure. The source/drain may cross over the plurality of fin-shaped channels and may be electrically connected to the plurality of fin-shaped channels. The methods may also include forming a metallic layer on an upper surface of the source/drain and forming a conductive contact on the metallic layer opposite the source/drain. The conductive contact may have a first length in a longitudinal direction of the metallic layer that is less than a second length of the metallic layer in the longitudinal direction of the metallic layer.

公开(公告)号：US20160071848A1

公开(公告)日：2016-03-10

申请号：US14834419

申请日：2015-08-24

Applicant: Rwik SENGUPTA ,  Mark S. RODDER

Inventor： Rwik SENGUPTA ,  Mark S. RODDER

IPC: H01L27/088 ,  H01L23/535 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0642 ,  H01L29/0847

Abstract: An embodiment includes a semiconductor device, comprising: a substrate; a continuous diffusion region disposed on the substrate; a first gate structure disposed on the continuous diffusion region; a second gate structure disposed on the continuous diffusion region; an isolation gate structure disposed between the first gate structure and the second gate structure and disposed adjacent to the both the first gate structure and the second gate structure; a first diffusion region of the continuous diffusion region disposed between the first gate structure and the isolation gate structure; a second diffusion region of the continuous diffusion region disposed between the second gate structure and the isolation gate structure; a conductive layer disposed on the first and second diffusion regions; and an isolation gate contact disposed over the isolation gate structure and electrically insulated from the first diffusion region.

Abstract translation: 实施例包括半导体器件，包括：衬底; 设置在所述基板上的连续扩散区域; 设置在所述连续扩散区上的第一栅极结构; 设置在所述连续扩散区上的第二栅极结构; 隔离栅极结构，设置在所述第一栅极结构和所述第二栅极结构之间并且邻近所述第一栅极结构和所述第二栅极结构设置; 所述连续扩散区域的第一扩散区域设置在所述第一栅极结构和所述隔离栅极结构之间; 所述连续扩散区域的第二扩散区域设置在所述第二栅极结构和所述隔离栅极结构之间; 布置在所述第一和第二扩散区上的导电层; 以及设置在隔离栅结构上并与第一扩散区电绝缘的隔离栅极触点。