公开(公告)号：US20160104787A1

公开(公告)日：2016-04-14

申请号：US14878230

申请日：2015-10-08

Applicant: Jorge A. Kittl ,  Ganesh Hegde ,  Rwik Sengupta ,  Borna J. Obradovic ,  Mark S. Rodder

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Rwik Sengupta ,  Borna J. Obradovic ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L29/417

CPC classification number: H01L29/665 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76843 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming a plurality of fin-shaped channels on a substrate, forming a gate structure crossing over the plurality of fin-shaped channels and forming a source/drain adjacent a side of the gate structure. The source/drain may cross over the plurality of fin-shaped channels and may be electrically connected to the plurality of fin-shaped channels. The methods may also include forming a metallic layer on an upper surface of the source/drain and forming a conductive contact on the metallic layer opposite the source/drain. The conductive contact may have a first length in a longitudinal direction of the metallic layer that is less than a second length of the metallic layer in the longitudinal direction of the metallic layer.

Abstract translation: 提供了形成半导体器件的方法。 所述方法可以包括在衬底上形成多个鳍形通道，形成跨越多个鳍形通道的栅极结构，并且在栅极结构的一侧形成源极/漏极。 源极/漏极可以跨越多个鳍状沟道并且可以电连接到多个鳍状沟道。 所述方法还可以包括在源极/漏极的上表面上形成金属层，并在与源极/漏极相对的金属层上形成导电接触。 导电接触可以在金属层的纵向方向上具有小于金属层在金属层的纵向方向上的第二长度的第一长度。

公开(公告)号：US10361195B2

公开(公告)日：2019-07-23

申请号：US14834419

申请日：2015-08-24

Applicant: Rwik Sengupta ,  Mark S. Rodder

Inventor： Rwik Sengupta ,  Mark S. Rodder

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/02

Abstract: An embodiment includes a semiconductor device, comprising: a substrate; a continuous diffusion region disposed on the substrate; a first gate structure disposed on the continuous diffusion region; a second gate structure disposed on the continuous diffusion region; an isolation gate structure disposed between the first gate structure and the second gate structure and disposed adjacent to the both the first gate structure and the second gate structure; a first diffusion region of the continuous diffusion region disposed between the first gate structure and the isolation gate structure; a second diffusion region of the continuous diffusion region disposed between the second gate structure and the isolation gate structure; a conductive layer disposed on the first and second diffusion regions; and an isolation gate contact disposed over the isolation gate structure and electrically insulated from the first diffusion region.

公开(公告)号：US10297673B2

公开(公告)日：2019-05-21

申请号：US14878230

申请日：2015-10-08

Applicant: Jorge A. Kittl ,  Ganesh Hegde ,  Rwik Sengupta ,  Borna J. Obradovic ,  Mark S. Rodder

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Rwik Sengupta ,  Borna J. Obradovic ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/285 ,  H01L23/485 ,  H01L29/78 ,  H01L29/165 ,  H01L21/768

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming a plurality of fin-shaped channels on a substrate, forming a gate structure crossing over the plurality of fin-shaped channels and forming a source/drain adjacent a side of the gate structure. The source/drain may cross over the plurality of fin-shaped channels and may be electrically connected to the plurality of fin-shaped channels. The methods may also include forming a metallic layer on an upper surface of the source/drain and forming a conductive contact on the metallic layer opposite the source/drain. The conductive contact may have a first length in a longitudinal direction of the metallic layer that is less than a second length of the metallic layer in the longitudinal direction of the metallic layer.

公开(公告)号：US10283638B2

公开(公告)日：2019-05-07

申请号：US15086015

申请日：2016-03-30

Applicant: Jorge A. Kittl ,  Ganesh Hegde ,  Robert C. Bowen ,  Mark S. Rodder

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack comprises a plurality of sacrificial layers in which each sacrificial layer comprises a first lattice parameter; and at least one channel layer comprising a second lattice parameter that is different from the first lattice parameter and in which each channel layer is disposed between and in contact with two sacrificial layers. The stack is formed on an underlayer in which a sacrificial layer is in contact with the underlayer. The underlayer comprises a third lattice parameter that substantially matches the lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were was allow to relax coherently.

公开(公告)号：US20150243756A1

公开(公告)日：2015-08-27

申请号：US14698402

申请日：2015-04-28

Applicant: Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

Inventor： Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L29/66

CPC classification number: H01L29/66522 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include InyGa1−yAs, and y is in a range of about 0.3 to about 0.5.

Abstract translation: 提供了形成finFET的方法。 所述方法可以包括在衬底上形成包括铟（In）的鳍状沟道区域，形成与衬底上的沟道区相邻的深源极/漏极区域，并在沟道区域和深度之间形成源极/漏极延伸区域 源/漏区。 源极/漏极延伸区域的相对侧壁可以分别接触沟道区域和深源极/漏极区域，并且源极/漏极延伸区域可以包括In y Ga 1-y As，y在约0.3至约0.5的范围内。

公开(公告)号：US09064699B2

公开(公告)日：2015-06-23

申请号：US14258704

申请日：2014-04-22

Applicant: Wei-E Wang ,  Mark S. Rodder ,  Robert C. Bowen

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Robert C. Bowen

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/02488 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/66795

Abstract: Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate.

Abstract translation: 提供了形成包括减少的位错缺陷的半导体图案的方法和使用这些方法形成的器件。 所述方法可以包括在衬底上形成氧化物层并在氧化物层和衬底中形成凹陷。 所述方法还可以包括在所述凹部中形成外延生长的半导体图案，所述外延生长的半导体图案在所述氧化物层和所述衬底之间的界面处接触所述衬底的侧壁，并且限定所述衬底的所述凹部中的空隙的上表面。

公开(公告)号：USD571642S1

公开(公告)日：2008-06-24

申请号：US29259967

申请日：2006-05-18

Applicant: Mark S. Rodder

Designer： Mark S. Rodder

公开(公告)号：US07371658B2

公开(公告)日：2008-05-13

申请号：US10870020

申请日：2004-06-17

Applicant: Rick L. Wise ,  Mark S. Rodder

Inventor： Rick L. Wise ,  Mark S. Rodder

IPC: H01L21/76 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76224 ,  H01L21/823807 ,  H01L21/823878

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having a buffer layer (133) located on sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract translation: 本发明提供一种沟槽隔离结构及其制造方法以及包括该沟槽隔离结构的集成电路的制造方法。 在一个实施例中，沟槽隔离结构（130）包括位于衬底（110）内的沟槽，沟槽具有位于其侧壁上的缓冲层（133）。 沟槽隔离结构（130）还包括位于缓冲层（133）上的阻挡层（135）和位于阻挡层（135）上方并且基本上填充沟槽的填充材料（138）。

公开(公告)号：US06352900B1

公开(公告)日：2002-03-05

申请号：US09618404

申请日：2000-07-18

Applicant: Manoj Mehrotra ,  Jerry Che-Jen Hu ,  Amitava Chatterjee ,  Mark S. Rodder

Inventor： Manoj Mehrotra ,  Jerry Che-Jen Hu ,  Amitava Chatterjee ,  Mark S. Rodder

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/28247

Abstract: A method for controlled oxide growth on transistor gates. A first film (40) is formed on a semiconductor substrate (10). The film is implanted with a first species and patterned to form a transistor gate (45) . The transistor gate (45) and the semiconductor substrate (10) is implanted with a second species and the transistor gate (45) oxidized to produce an oxide film (80) on the side surface of the transistor gate (45).

Abstract translation: 一种在晶体管栅极上控制氧化物生长的方法。 第一膜（40）形成在半导体衬底（10）上。 该膜植入第一种并图案化以形成晶体管栅极（45）。 晶体管栅极（45）和半导体衬底（10）被注入第二种类，并且晶体管栅极（45）被氧化以在晶体管栅极（45）的侧表面上产生氧化物膜（80）。

公开(公告)号：US06228725B1

公开(公告)日：2001-05-08

申请号：US09281543

申请日：1999-03-30

Applicant: Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

Inventor： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

IPC: H01L21336

CPC classification number: H01L29/66575 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/7838

Abstract: A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).

Abstract translation: 形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。 晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。 通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。 第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。