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公开(公告)号：US10297673B2
公开(公告)日：2019-05-21
申请号：US14878230
申请日：2015-10-08
IPC分类号： H01L29/66 , H01L29/417 , H01L21/285 , H01L23/485 , H01L29/78 , H01L29/165 , H01L21/768
摘要： Methods of forming a semiconductor device are provided. The methods may include forming a plurality of fin-shaped channels on a substrate, forming a gate structure crossing over the plurality of fin-shaped channels and forming a source/drain adjacent a side of the gate structure. The source/drain may cross over the plurality of fin-shaped channels and may be electrically connected to the plurality of fin-shaped channels. The methods may also include forming a metallic layer on an upper surface of the source/drain and forming a conductive contact on the metallic layer opposite the source/drain. The conductive contact may have a first length in a longitudinal direction of the metallic layer that is less than a second length of the metallic layer in the longitudinal direction of the metallic layer.
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2.发明申请METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE CONTACTS ON SOURCE/DRAINS 审中-公开形成半导体器件的方法，包括在源/漏极上的导电接触公开(公告)号：US20160104787A1
公开(公告)日：2016-04-14
申请号：US14878230
申请日：2015-10-08
IPC分类号： H01L29/66 , H01L29/417
CPC分类号： H01L29/665 , H01L21/28512 , H01L21/28518 , H01L21/76843 , H01L23/485 , H01L29/165 , H01L29/41725 , H01L29/66545 , H01L29/66795 , H01L29/7848
摘要： Methods of forming a semiconductor device are provided. The methods may include forming a plurality of fin-shaped channels on a substrate, forming a gate structure crossing over the plurality of fin-shaped channels and forming a source/drain adjacent a side of the gate structure. The source/drain may cross over the plurality of fin-shaped channels and may be electrically connected to the plurality of fin-shaped channels. The methods may also include forming a metallic layer on an upper surface of the source/drain and forming a conductive contact on the metallic layer opposite the source/drain. The conductive contact may have a first length in a longitudinal direction of the metallic layer that is less than a second length of the metallic layer in the longitudinal direction of the metallic layer.
摘要翻译： 提供了形成半导体器件的方法。 所述方法可以包括在衬底上形成多个鳍形通道，形成跨越多个鳍形通道的栅极结构，并且在栅极结构的一侧形成源极/漏极。 源极/漏极可以跨越多个鳍状沟道并且可以电连接到多个鳍状沟道。 所述方法还可以包括在源极/漏极的上表面上形成金属层，并在与源极/漏极相对的金属层上形成导电接触。 导电接触可以在金属层的纵向方向上具有小于金属层在金属层的纵向方向上的第二长度的第一长度。
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公开(公告)号：US10147793B2
公开(公告)日：2018-12-04
申请号：US14227812
申请日：2014-03-27
IPC分类号： H01L29/417 , H01L29/66 , H01L29/78
摘要： A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain contact in the recess provided by increased depth may be less than an incremental increase in total resistance due to the increase in the vertical portion of the source/drain contact at the increased depth.
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4.发明申请FINFET DEVICES INCLUDING RECESSED SOURCE/DRAIN REGIONS HAVING OPTIMIZED DEPTHS AND METHODS OF FORMING THE SAME 审中-公开FINFET装置，包括具有优化深度的被吸收源/排水区及其形成方法公开(公告)号：US20150035074A1
公开(公告)日：2015-02-05
申请号：US14227812
申请日：2014-03-27
IPC分类号： H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L29/41791 , H01L29/785
摘要： A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain contact in the recess provided by increased depth may be less than an incremental increase in total resistance due to the increase in the vertical portion of the source/drain contact at the increased depth.
摘要翻译： finFET器件可以包括具有最佳深度的源极/漏极接触凹部，超过该源极/漏极接触凹部，由增加的深度提供的凹部中的源极/漏极接触件的水平部分的扩展电阻值的增量减小可以小于 由于在增加的深度处源极/漏极接触件的垂直部分的增加导致的总电阻。
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5.发明申请INTEGRATED CIRCUIT DEVICES INCLUDING FINFETS AND METHODS OF FORMING THE SAME 有权包括FINFET的集成电路器件及其形成方法公开(公告)号：US20150243756A1
公开(公告)日：2015-08-27
申请号：US14698402
申请日：2015-04-28
IPC分类号： H01L29/66
CPC分类号： H01L29/66522 , H01L21/3086 , H01L21/823431 , H01L21/823821 , H01L29/165 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include InyGa1−yAs, and y is in a range of about 0.3 to about 0.5.
摘要翻译： 提供了形成finFET的方法。 所述方法可以包括在衬底上形成包括铟（In）的鳍状沟道区域，形成与衬底上的沟道区相邻的深源极/漏极区域，并在沟道区域和深度之间形成源极/漏极延伸区域 源/漏区。 源极/漏极延伸区域的相对侧壁可以分别接触沟道区域和深源极/漏极区域，并且源极/漏极延伸区域可以包括In y Ga 1-y As，y在约0.3至约0.5的范围内。
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6.发明授权Integrated circuit devices including FinFETS and methods of forming the same 有权包括FinFETS的集成电路器件及其形成方法公开(公告)号：US09178045B2
公开(公告)日：2015-11-03
申请号：US14489965
申请日：2014-09-18
IPC分类号： H01L29/66 , H01L29/16 , H01L21/265 , H01L21/266 , H01L21/306 , H01L21/308 , H01L21/82 , H01L29/161 , H01L29/165 , H01L21/8234 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/26506 , H01L21/26513 , H01L21/266 , H01L21/30604 , H01L21/308 , H01L21/3086 , H01L21/823431 , H01L21/823821 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/7848 , H01L29/785
摘要： Integrated circuit devices including fin field-effect transistors (finFETs) and methods of forming the same are provided. The methods may include forming a fin-shaped channel region including germanium on a substrate and forming a source/drain region adjacent the channel region on the substrate. The methods may further include forming a barrier layer contacting sidewalls of the channel region and the source/drain region, and the barrier layer may include SixGe1-x, and x may be in a range of about 0.05 to about 0.2.
摘要翻译： 提供包括鳍状场效应晶体管（finFET）的集成电路器件及其形成方法。 所述方法可以包括在衬底上形成包括锗的鳍状沟道区，并形成与衬底上的沟道区相邻的源极/漏极区。 所述方法还可以包括形成与沟道区域和源极/漏极区域的侧壁接触的阻挡层，并且阻挡层可以包括SixGe1-x，x可以在约0.05至约0.2的范围内。
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7.发明申请CRYSTALLINE MULTIPLE-NANOSHEET STRAINED CHANNEL FETS AND METHODS OF FABRICATING THE SAME 有权晶体多晶纳米管应变通道FET及其制备方法公开(公告)号：US20150295084A1
公开(公告)日：2015-10-15
申请号：US14729652
申请日：2015-06-03
IPC分类号： H01L29/78 , H01L29/49 , H01L29/423
CPC分类号： H01L29/7845 , B82Y40/00 , H01L29/0673 , H01L29/20 , H01L29/42392 , H01L29/517 , H01L29/775 , H01L29/785 , H01L29/78681 , H01L29/78696
摘要： A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.
摘要翻译： 场效应晶体管包括具有应变晶体半导体沟道区的主体层，以及沟道区上的栅叠层。 栅极堆叠包括与沟道区域晶格失配的晶体半导体栅极层，以及栅极层和沟道区域之间的晶体栅极介电层。 还讨论了相关设备和制造方法。
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8.发明申请SEMICONDUCTOR DEVICES WITH STRUCTURES FOR SUPPRESSION OF PARASITIC BIPOLAR EFFECT IN STACKED NANOSHEET FETS AND METHODS OF FABRICATING THE SAME 有权具有抑制堆叠纳米晶体FET中PARASITIC双极效应的结构的半导体器件及其制造方法公开(公告)号：US20160163796A1
公开(公告)日：2016-06-09
申请号：US14952152
申请日：2015-11-25
CPC分类号： H01L29/0676 , B82B3/0014 , B82Y10/00 , H01L29/0642 , H01L29/0653 , H01L29/0665 , H01L29/16 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/785 , H01L29/78618 , H01L29/78681 , H01L29/78684 , H01L29/78696
摘要： A device may include a nanosheet field effect transistor (FET) that may include a substrate, a well that is doped with impurities at a surface of the substrate, a channel including a plurality of stacked nanosheets, a gate, a conductive material, and an isolation layer. Ones of the plurality of stacked nanosheets may include a semiconductor material that may be doped with impurities of the same conductivity type as the impurities of the well. The conductive material may be adjacent the plurality of nanosheets and may electrically connect ones of the plurality of nanosheets to the well. The isolation layer may electrically insulate the well from the workfunction metal.
摘要翻译： 器件可以包括纳米片状场效应晶体管（FET），其可以包括衬底，在衬底的表面上掺杂有杂质的阱，包括多个堆叠的纳米片，沟道，导电材料和 隔离层 多个堆叠的纳米片的一部分可以包括半导体材料，其可掺杂与阱的杂质相同的导电类型的杂质。 导电材料可以与多个纳米片相邻，并且可以将多个纳米片中的一个纳米片电连接到该孔。 隔离层可以将孔与功函数金属电绝缘。
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9.发明申请FINFET SEMICONDUCTOR DEVICES INCLUDING RECESSED SOURCE-DRAIN REGIONS ON A BOTTOM SEMICONDUCTOR LAYER AND METHODS OF FABRICATING THE SAME 有权FINFET半导体器件，包括底层半导体层上的残留源区域及其制造方法公开(公告)号：US20150145003A1
公开(公告)日：2015-05-28
申请号：US14534453
申请日：2014-11-06
IPC分类号： H01L29/78 , H01L27/092 , H01L27/12 , H01L29/66 , H01L29/165
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7848
摘要： FinFET semiconductor devices and methods of forming the same are provided. The finFET semiconductor devices may include an insulator layer, a bottom semiconductor layer on the insulator layer, a channel fin on the bottom semiconductor layer, a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, and a drain region on the bottom semiconductor layer and adjacent a second side of the channel fin opposite the first side.
摘要翻译： 提供FinFET半导体器件及其形成方法。 finFET半导体器件可以包括绝缘体层，绝缘体层上的底部半导体层，底部半导体层上的沟道鳍片，底部半导体层上的源极区域和与沟道鳍片的第一侧相邻的源区域，以及漏极区域 在底部半导体层上并且与第一侧相对的沟槽的第二侧相邻。
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10.发明申请INTEGRATED CIRCUIT DEVICES INCLUDING FINFETS AND METHODS OF FORMING THE SAME 有权包括FINFET的集成电路器件及其形成方法公开(公告)号：US20150093868A1
公开(公告)日：2015-04-02
申请号：US14489965
申请日：2014-09-18
IPC分类号： H01L29/66 , H01L29/161 , H01L29/165 , H01L21/308 , H01L21/265 , H01L21/266 , H01L21/306 , H01L29/16 , H01L21/02
CPC分类号： H01L29/66795 , H01L21/26506 , H01L21/26513 , H01L21/266 , H01L21/30604 , H01L21/308 , H01L21/3086 , H01L21/823431 , H01L21/823821 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/7848 , H01L29/785
摘要： Integrated circuit devices including fin field-effect transistors (finFETs) and methods of forming the same are provided. The methods may include forming a fin-shaped channel region including germanium on a substrate and forming a source/drain region adjacent the channel region on the substrate. The methods may further include forming a barrier layer contacting sidewalls of the channel region and the source/drain region, and the barrier layer may include SixGe1-x, and x may be in a range of about 0.05 to about 0.2.
摘要翻译： 提供包括鳍状场效应晶体管（finFET）的集成电路器件及其形成方法。 所述方法可以包括在衬底上形成包括锗的鳍状沟道区，并形成与衬底上的沟道区相邻的源极/漏极区。 所述方法还可以包括形成与沟道区域和源极/漏极区域的侧壁接触的阻挡层，并且阻挡层可以包括SixGe1-x，x可以在约0.05至约0.2的范围内。
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