公开(公告)号：US12267115B2

公开(公告)日：2025-04-01

申请号：US18013937

申请日：2021-06-21

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Chengwei Jia

IPC: H04B17/00 ,  H04B17/12 ,  H04B17/14 ,  H04B17/21

Abstract: The present disclosure provides a method for determining a target initial phase, including: acquiring a voltage amplitude of a system direct-current offset signal of a phased array system corresponding to N target channels to be calibrated; respectively acquiring voltage amplitudes of a total direct-current offset signal under different initial phases; and calculating voltage amplitudes of a mixed direct-current offset signal of the N target channels under the different initial phases, and taking an initial phase of the N target channels, when the voltage amplitude of the mixed direct-current offset signal reaches the maximum value, as a target initial phase of the N target channels. The present disclosure further provides a phase calibration method, an apparatus for determining an initial phase, and an antenna system.

公开(公告)号：US12243188B2

公开(公告)日：2025-03-04

申请号：US17618534

申请日：2020-04-16

Applicant: SANECHIPS TECHNOLOGY CO., LTD

Inventor： Dehui Kong ,  Ke Xu ,  Xiao Zhang ,  Hong Wang ,  Bin Han ,  Ning Wang ,  Xin Liu ,  Guoning Lu ,  Fang Zhu

IPC: G06K9/00 ,  G06T3/4046 ,  G06T3/4053

Abstract: The present application provides an image processing method, an image processing device, a computer storage medium and a terminal, the image processing method includes: determining convolution kernels of at least two sizes for feature extraction; performing sparsity constraint for the determined convolution kernels of at least two sizes for feature extraction through a preset objective function; and performing feature extraction on an image based on the convolution kernels subjected to the sparsity constraint.

公开(公告)号：US20250069188A1

公开(公告)日：2025-02-27

申请号：US18721427

申请日：2022-02-28

Applicant: SANECHIPS TECHNOLOGY CO.,LTD

Inventor： Yan XIANG ,  Dehui KONG ,  Ke XU

IPC: G06T3/4046 ,  G06T3/4053

Abstract: Provided in the embodiments of the present disclosure are a method and apparatus for training an image reconstruction model, a storage medium, and an electronic device. The method includes: acquiring a target teacher image reconstruction model; training, by using the target sample image set, a student image reconstruction model to be trained, and ending the training until a target loss value satisfies a second preset loss condition, so as to obtain a target student image reconstruction model, wherein the target loss value is a loss value determined according to a first loss value and a second loss value, and the second loss value is a loss value determined according to a difference value between a predicted value and a real value respectively determined by the student image reconstruction model to be trained and the target teacher image reconstruction model.

公开(公告)号：US20250015812A1

公开(公告)日：2025-01-09

申请号：US18710843

申请日：2022-03-19

Applicant: SANECHIPS TECHNOLOGY CO.,LTD

Inventor： Hejie YU

IPC: H03M1/12 ,  G11C7/16 ,  H03L7/085

Abstract: Provided are a sampling circuit and a sampling method. The circuit comprises: a generator, configured to generate a first loopback pulse signal; a loopback selection module, configured to establish a plurality of loopback links according to a pre-configured connection combination; a link loopback pulse signal transmission module, configured to receive the first loopback pulse signal, and transmit the first loopback pulse signal in the plurality of loopback links; a loopback sampling module, connected to the link loopback pulse signal transmission module and configured to determine, from the plurality of loopback links, a target loopback link on which sampling is to be performed, and sample first link data that is on the target loopback link and passes through a target sampling point, and a sampling storage module, connected to the loopback sampling module and configured to store sampling data in a random access memory.

公开(公告)号：US20240356551A1

公开(公告)日：2024-10-24

申请号：US18575154

申请日：2022-03-02

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Wentao ZHU ,  Yunfeng CHANG ,  Hao LUO ,  Yuhu CHEN ,  Haipeng ZHU ,  Yumei DIAO

IPC: H03K19/0185 ,  H03L7/08 ,  H03M1/00

CPC classification number: H03K19/018507 ,  H03L7/08 ,  H03M1/00

Abstract: Provided in the present disclosure is a clock receiving circuit. The clock receiving circuit comprises a common-mode voltage adjustment module, an amplitude amplification module and a level conversion module. The common-mode voltage adjustment module comprises an n-type signal conversion unit, a high-level n-type signal output end, a low-level n-type signal output end, a p-type signal conversion unit, a high-level p-type signal output end and a low-level p-type signal output end. The amplitude amplification module comprises a p-type current source transistor, an n-type current source transistor, a p-type transistor differential pair, an n-type transistor differential pair and a bias control unit. The level conversion module is used for converting, into a CMOS level signal, a CML level signal which is output by the amplitude amplification circuit. Further provided in the present disclosure is an electronic device comprising the clock receiving circuit.

公开(公告)号：US20240349163A1

公开(公告)日：2024-10-17

申请号：US18685579

申请日：2022-04-20

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Dingming ZHANG

IPC: H04W40/20 ,  H04L25/02

CPC classification number: H04W40/20 ,  H04L25/0242

Abstract: The present disclosure provides signal detection method and apparatus, an electronic device, and a computer readable storage medium. The signal detection method includes: dividing nodes in a MT-th transmitting layer into M blocks, with MT representing a number of transmitting layers and M being an integer greater than or equal to 2; searching for a path corresponding to a central node of each block to obtain M paths, with the central node of each block being a node corresponding to a path with a smallest Euclidean distance among all nodes of the block; selecting N paths with smallest Euclidean distances from the M paths, with N being an integer less than M; searching for paths corresponding to all nodes of blocks where N nodes respectively corresponding to the N paths are located to obtain P paths; and selecting a path with a smallest Euclidean distance from the P paths.

公开(公告)号：US20240323120A1

公开(公告)日：2024-09-26

申请号：US18572948

申请日：2022-06-22

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Siyu WANG ,  Fengsong LIU ,  Zhihua ZHU ,  Hengqi LIU

IPC: H04L45/7453

CPC classification number: H04L45/7453

Abstract: Embodiments of the present disclosure provide a packet matching method and apparatus, a storage medium, and an electronic device. The method includes: determining multiple Hash calculation results corresponding to a key value of a packet; indexing addresses in multiple counter groups respectively according to the multiple Hash calculation results, so as to determine multiple counters, wherein one counter is indexed in one counter group; determining one target counter from the multiple counters; acquiring a target entry at a corresponding position of an off-chip memory according to the address of the target counter; in a case where the target entry is equal to the key value, determining that the packet matches the target entry.

公开(公告)号：US20240322772A1

公开(公告)日：2024-09-26

申请号：US18694227

申请日：2022-03-19

Applicant: SANECHIPS TECHNOLOGY CO.,LTD

Inventor： Yi LIU ,  Yong WANG

IPC: H03F3/45 ,  H03G3/30 ,  H04B1/04

CPC classification number: H03F3/45076 ,  H03G3/3036 ,  H03F2200/451 ,  H03G2201/103 ,  H03G2201/307 ,  H04B1/04 ,  H04B2001/045

Abstract: Provided are a low-phase-shift variable-gain amplifier and a method for processing a radio frequency signal. The low-phase-shift variable-gain amplifier comprises: a differential cascode amplification circuit, which comprises a common-source transistor and a common-gate transistor, wherein a gate stage of the common-source transistor is connected to a first bias voltage via a target resistor, and a gate stage of the common-gate transistor is connected to a second bias voltage; a current-steering structure, wherein one end of the current-steering structure is connected between the common-source transistor and the common-gate transistor, a third current signal outputted by the current-steering structure is used to adjust a gain of the differential cascode amplification circuit; and a phase compensation circuit, wherein one end of the phase compensation circuit is connected between the common-source transistor and the common-gate transistor.

公开(公告)号：US20240267269A1

公开(公告)日：2024-08-08

申请号：US18564068

申请日：2022-03-21

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Gang WU ,  Junling ZHANG

IPC: H04L27/00 ,  H04B7/0452

CPC classification number: H04L27/0012 ,  H04B7/0452

Abstract: Provided are a multi-user multiple-input multiple-output detection method and apparatus, an electronic device, and a computer-readable storage medium. The method includes: in a case where it is determined that received data includes data for first user equipment and data for at least one second user equipment, determining a first detection method according to a modulation mode of the first user equipment (100); and performing multi-user joint detection on the received data with the first detection method (101).

公开(公告)号：US12057852B2

公开(公告)日：2024-08-06

申请号：US17772970

申请日：2020-10-29

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Gang Wu

IPC: H03M1/06

CPC classification number: H03M1/0607

Abstract: Provided are a sampling clock phase mismatch error estimation method and apparatus, and a storage medium. This sampling clock phase mismatch error estimation method includes: a proportional relation between an estimation operator of a modular square subtraction method corresponding to each frequency interval of multiple frequency intervals and a sampling clock phase mismatch error of a time-interleaved analog to digital converter (TIADC) is acquired; a slope and an offset value of a fitting proportion line segment are counted; and a slope of a proportion line segment corresponding to a real-time estimation frequency is converted, and an offset value corresponding to the real-time estimation frequency is estimated through an interpolation according to a counted slope and a counted offset value, and the actual value of the sampling clock phase mismatch error is estimated according to a converted slope and an offset value estimated through the interpolation.