公开(公告)号：US20150206738A1

公开(公告)日：2015-07-23

申请号：US14159970

申请日：2014-01-21

申请人： SEMATECH, Inc.

发明人： Abbas Rastegar

IPC分类号： H01L21/02 ,  B08B3/12

CPC分类号： B08B3/12 ,  B06B1/0276 ,  B06B1/0622 ,  B06B2201/71 ,  C11D11/0047 ,  C11D11/007 ,  H01L21/67051

摘要： An apparatus, system, and method for cleaning surfaces is presented. One embodiment of the system includes an array of surface acoustic wave (SAW) transducers coupled to a substrate. The system may include a positioning mechanism coupled to at least one of a target surface or the array of SAW transducers, and configured to position the array of SAW transducers within an effective cleaning distance of a target surface. The system may also include a cleaning liquid supply arranged to provide cleaning liquid for coupling the array of SAW transducers to the target surface. The system may further include a controller coupled to the array of SAW transducers and configured to activate the array of SAW transducers. At least one of the SAW transducers may be formed to focus cleaning liquid on a focal point and jet cleaning liquid in a direction substantially out of the place of the SAW transducer.

摘要翻译： 提出了一种用于清洁表面的设备，系统和方法。 该系统的一个实施例包括耦合到衬底的表面声波（SAW）传感器的阵列。 该系统可以包括耦合到目标表面或SAW换能器阵列中的至少一个的定位机构，并且被配置为将SAW换能器阵列置于目标表面的有效清洁距离内。 该系统还可以包括布置成提供用于将SAW换能器阵列耦合到目标表面的清洁液体的清洁液体供应。 该系统还可以包括耦合到SAW换能器阵列并被配置为激活SAW换能器阵列的控制器。 可以形成至少一个SAW换能器，以将清洁液体聚焦在焦点上，并将射流清洁液体基本上不在SAW换能器的位置。

公开(公告)号：US20150111372A1

公开(公告)日：2015-04-23

申请号：US14519250

申请日：2014-10-21

申请人： Sematech, Inc.

发明人： Robert TIECKELMANN ,  Wei-Yip LOH ,  Rinus Tek Po LEE

IPC分类号： H01L21/225

CPC分类号： H01L21/2254 ,  H01L21/2225 ,  H01L21/228

摘要： Provided are methods for preparing a doped silicon material. The methods include contacting a surface of a silicon material with a dopant solution comprising a dopant-containing compound selected from a phosphorus-containing compound and an arsenic-containing compound, to form a layer of dopant material on the surface; and diffusing the dopant into the silicon material, thereby forming the doped silicon material, wherein the doped silicon material has a sheet resistance (Rs) of less than or equal to 2,000 Ω/sq.

摘要翻译： 提供了制备掺杂硅材料的方法。 所述方法包括使硅材料的表面与包含选自含磷化合物和含砷化合物的掺杂剂化合物的掺杂剂溶液接触，以在表面上形成掺杂剂材料层; 并将掺杂剂扩散到硅材料中，从而形成掺杂的硅材料，其中掺杂硅材料的薄层电阻（Rs）小于或等于2,000＆OHgr / sq。

公开(公告)号：US20150158056A1

公开(公告)日：2015-06-11

申请号：US14098713

申请日：2013-12-06

申请人： SEMATECH, Inc.

发明人： Abbas RASTEGAR

IPC分类号： B08B7/02 ,  B08B7/04 ,  B08B3/12 ,  B08B7/00

CPC分类号： B08B7/026 ,  B08B3/12 ,  B08B7/0035 ,  H01L21/67057 ,  H01L21/67115

摘要： A cleaning tool facilitating removal of particles from a surface is provided which includes an acoustic wave generator and one or more light-emitting diodes. The acoustic wave generator, which is configured to direct acoustic waves towards the surface to be cleaned, may include an acoustic transducer that facilitates generating the acoustic waves, and an acoustic coupler substrate through which the acoustic waves propagate. The light-emitting diode(s), which is configured to direct light towards the surface to be cleaned, is coupled to the acoustic coupler substrate of the acoustic wave generator. The acoustic wave generator and the light-emitting diode(s) are spaced from the surface to be cleaned, and are configured to selectively concurrently direct overlapping, at least partially, acoustic waves and light energy towards the surface to facilitate removal of particles by breaking bonds between the particles and the surface.

摘要翻译： 提供了一种便于从表面除去颗粒的清洁工具，其包括声波发生器和一个或多个发光二极管。 声波发生器被配置成将声波引向待清洁的表面，可以包括有助于产生声波的声学换能器以及声波传播通过声学耦合器衬底。 配置为将光引向待清洁表面的发光二极管耦合到声波发生器的声耦合器衬底。 声波发生器和发光二极管与要清洁的表面间隔开，并且被配置为选择性地同时地向表面重叠至少部分地将声波和光能重叠，以便通过断开来去除颗粒 颗粒与表面之间的结合。

公开(公告)号：US20150062546A1

公开(公告)日：2015-03-05

申请号：US14537106

申请日：2014-11-10

申请人： SEMATECH, INC.

发明人： Abbas RASTEGAR

IPC分类号： G03F7/20 ,  H01L21/67

CPC分类号： G03F7/70916 ,  G03F1/66 ,  G03F1/68 ,  G03F7/70841 ,  H01L21/6719 ,  Y10S269/903

摘要： An apparatus is provided for protecting a surface of interest from particle contamination, and particularly, during transitioning of the surface between atmospheric pressure and vacuum. The apparatus includes a chamber configured to receive the surface, and a protector plate configured to reside within the chamber with the surface, and inhibit particle contamination of the surface. A support mechanism is also provided suspending the protector plate away from an inner surface of the chamber. The support mechanism holds the protector plate within the chamber in spaced, opposing relation to the surface to provide a gap between the protector plate and the surface which presents a diffusion barrier to particle migration into the gap and onto the surface, thereby inhibiting particle contamination of the surface.

摘要翻译： 提供了一种用于保护感兴趣的表面免受颗粒污染的装置，特别是在大气压力和真空之间的表面过渡期间。 所述设备包括被配置为容纳所述表面的室，以及被配置成与所述表面一起驻留在所述室内的保护板，并且抑制所述表面的颗粒污染。 还提供了一种支撑机构，其将保护板悬挂在室的内表面之外。 支撑机构将保护板保持在腔内与表面间隔开的相对关系，以在保护板和表面之间提供间隙，该间隙对于颗粒迁移到间隙中并在表面上具有扩散阻挡，从而抑制颗粒污染 表面。

公开(公告)号：US08865376B2

公开(公告)日：2014-10-21

申请号：US13790288

申请日：2013-03-08

申请人： Sematech, Inc. ,  Intel Corporation

发明人： Vibhu Jindal ,  Frank Goodwin ,  Patrick A. Kearney ,  Eric M. Panning

IPC分类号： G03F1/22 ,  G03F1/24 ,  G03F1/68

CPC分类号： G03F1/22

摘要： Methods are provided for fabricating a process structure, such as a mask or mask blank. The methods include, for instance: providing a silicon substrate; forming a multi-layer, extreme ultra-violet lithography (EUVL) structure over the silicon substrate; subsequent to forming the multi-layer EUVL structure over the crystalline substrate, reducing a thickness of the silicon substrate; and attaching a low-thermal-expansion material (LTEM) substrate to one of the multi-layer EUVL structure, or the reduced silicon substrate. In one implementation, the silicon substrate is a silicon wafer with a substantially defect-free surface upon which the multi-layer EUVL structure is formed. The multi-layer EUVL structure may include multiple bi-layers of a first material and a second material, as well as a capping layer, and optionally, an absorber layer, where the absorber layer is patternable to facilitating forming a EUVL mask from the process structure.

摘要翻译： 提供了用于制造诸如掩模或掩模坯料的工艺结构的方法。 所述方法包括例如：提供硅衬底; 在硅衬底上形成多层，极紫外光刻（EUVL）结构; 随后在晶体衬底上形成多层EUVL结构，减小硅衬底的厚度; 以及将低热膨胀材料（LTEM）衬底附接到多层EUVL结构之一或还原硅衬底。 在一个实施方案中，硅衬底是具有基本无缺陷表面的硅晶片，在其上形成多层EUVL结构。 多层EUVL结构可以包括第一材料和第二材料的多个双层，以及覆盖层和任选的吸收层，其中吸收层可图案化以便于从该过程形成EUVL掩模 结构体。

公开(公告)号：US20140183597A1

公开(公告)日：2014-07-03

申请号：US13729592

申请日：2012-12-28

申请人： SEMATECH, INC.

发明人： Rinus Tek Po LEE ,  Tae Woo KIM ,  Man Hoi WONG ,  Richard HILL

IPC分类号： H01L29/205

CPC分类号： H01L29/205 ,  H01L21/28575 ,  H01L29/452 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66522

摘要： Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.

摘要翻译： 具有包括n型III-V半导体材料的第一层和包括M（InP）（InGaAs）合金）的第二层的半导体结构，其中M选自Ni，Pt，Pd，Co，Ti，Zr，Y， Mo，Ru，Ir，Sb，In，Dy，Tb，Er，Yb和Te及其组合。 半导体结构在第一和第二层之间具有基本平坦的界面。 还公开了制造半导体结构的方法，以及降低接触面的界面粗糙度和/或薄层电阻的方法。

公开(公告)号：US20150333128A1

公开(公告)日：2015-11-19

申请号：US14277887

申请日：2014-05-15

申请人： Sematech, Inc.

发明人： Rinus LEE ,  Wei-Yip LOH ,  Robert TIECKELMANN

IPC分类号： H01L29/207 ,  H01L29/66 ,  H01L21/324 ,  H01L29/78

CPC分类号： H01L29/207 ,  H01L21/2258 ,  H01L21/324 ,  H01L29/66477 ,  H01L29/78

摘要： Provided are methods of fabricating a semiconductor structure. The methods include providing a III-V semiconductor substrate selected from InGaAs and InAs, introducing an n-type dopant selected from S, Se, and Te directly onto a surface of the III-V semiconductor substrate, introducing a co-dopant selected from N and P directly onto a surface of the III-V semiconductor substrate, and diffusing the n-type and co-dopant into the III-V semiconductor substrate, thereby forming an n-doped III-V semiconductor substrate containing the n-type dopant and the co-dopant. The methods produce inventive semiconductor structures, and devices that include the semiconductor structure.

摘要翻译： 提供制造半导体结构的方法。 所述方法包括提供选自InGaAs和InAs的III-V半导体衬底，将选自S，Se和Te的n型掺杂剂直接引入到III-V半导体衬底的表面上，引入选自N 和P直接在III-V半导体衬底的表面上，并将n型和辅助掺杂剂扩散到III-V半导体衬底中，从而形成含有n型掺杂剂的n掺杂III-V半导体衬底，以及 共掺杂物。 该方法产生本发明的半导体结构，以及包括半导体结构的器件。

公开(公告)号：US20140255828A1

公开(公告)日：2014-09-11

申请号：US13790288

申请日：2013-03-08

申请人： SEMATECH, INC. ,  INTEL CORPORATION

发明人： Vibhu JINDAL ,  Frank GOODWIN ,  Patrick A. KEARNEY ,  Eric M. PANNING

IPC分类号： G03F1/22

CPC分类号： G03F1/22

摘要： Methods are provided for fabricating a process structure, such as a mask or mask blank. The methods include, for instance: providing a silicon substrate; forming a multi-layer, extreme ultra-violet lithography (EUVL) structure over the silicon substrate; subsequent to forming the multi-layer EUVL structure over the crystalline substrate, reducing a thickness of the silicon substrate; and attaching a low-thermal-expansion material (LTEM) substrate to one of the multi-layer EUVL structure, or the reduced silicon substrate. In one implementation, the silicon substrate is a silicon wafer with a substantially defect-free surface upon which the multi-layer EUVL structure is formed. The multi-layer EUVL structure may include multiple bi-layers of a first material and a second material, as well as a capping layer, and optionally, an absorber layer, where the absorber layer is patternable to facilitating forming a EUVL mask from the process structure.

摘要翻译： 提供了用于制造诸如掩模或掩模坯料的工艺结构的方法。 所述方法包括例如：提供硅衬底; 在硅衬底上形成多层，极紫外光刻（EUVL）结构; 随后在晶体衬底上形成多层EUVL结构，减小硅衬底的厚度; 以及将低热膨胀材料（LTEM）衬底附接到多层EUVL结构之一或还原硅衬底。 在一个实施方案中，硅衬底是具有基本无缺陷表面的硅晶片，在其上形成多层EUVL结构。 多层EUVL结构可以包括第一材料和第二材料的多个双层，以及覆盖层和任选的吸收层，其中吸收层可图案化以便于从该过程形成EUVL掩模 结构体。

公开(公告)号：US20140123997A1

公开(公告)日：2014-05-08

申请号：US14035709

申请日：2013-09-24

申请人： Sematech, Inc.

发明人： Abbas Rastegar

IPC分类号： H01L21/67 ,  H01L21/02

CPC分类号： H01L21/67046 ,  B06B1/0276 ,  B06B1/0622 ,  B06B2201/20 ,  B06B2201/55 ,  B06B2201/71 ,  B08B3/12 ,  H01L21/02041

摘要： An apparatus, system, and method for a Gigasonic Brush for cleaning surfaces is presented. One embodiment of the system includes an array of acoustic transducers coupled to a substrate where the individual acoustic transducers have sizes in the range of 9 um2 to 250,000 um2. The system may include a positioning mechanism coupled to at least one of a target surface or the array of acoustic transducers, and configured to position the array of acoustic transducers within 1 millimeter of a target surface. The system may also include a cleaning liquid supply arranged to provide cleaning liquid for coupling the array of acoustic transducers to the target surface. The system may further include a controller coupled to the array of acoustic transducers and configured to activate the array of acoustic transducers.

摘要翻译： 介绍了一种用于清洁表面的Gigasonic Brush的设备，系统和方法。 该系统的一个实施例包括耦合到衬底的声学换能器阵列，其中各个声学换能器的尺寸在9um2至250,000um2的范围内。 系统可以包括耦合到目标表面或声换能器阵列中的至少一个的定位机构，并且被配置为将声换能器阵列定位在目标表面的1毫米内。 该系统还可以包括布置成提供用于将声换能器阵列耦合到目标表面的清洁液体的清洁液体供应。 系统还可以包括耦合到声换能器阵列并被配置为激活声换能器阵列的控制器。

公开(公告)号：US20130230954A1

公开(公告)日：2013-09-05

申请号：US13856649

申请日：2013-04-04

申请人： SEMATECH, INC.

发明人： Wei-Yip Loh ,  Brian Coss ,  Kanghoon Jeon

IPC分类号： H01L29/66

CPC分类号： H01L29/66477 ,  H01L29/7391 ,  H01L29/78

摘要： Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide.

摘要翻译： 在源极和漏极区之间具有突变结的水平和垂直隧道场效应晶体管（TFET）增加了载流子（例如，电子和空穴）的直接隧穿的概率。 增加的概率允许在具有突变结的TFET中更高的电流可实现。 可以通过在源极和漏极区域之间的电流路径中放置介电层或电介质层和半导体层来形成突变结。 电介质层可以是低介电常数氧化物，例如氧化硅，氧化镧，氧化锆或氧化铝。