公开(公告)号：US20040096964A1

公开(公告)日：2004-05-20

申请号：US10706246

申请日：2003-11-12

Applicant: STMicroelectronics S.r.1.

Inventor： Ubaldo Mastromattteo ,  Flavio Villa ,  Gabriele Barlocchi

IPC: C12M001/34 ,  C12M001/38

CPC classification number: B65D73/00 ,  A01G9/026 ,  B01J19/0093 ,  B01J2219/00873 ,  B01J2219/00961 ,  B01L3/5025 ,  B01L3/502707 ,  B01L3/502715 ,  B01L7/52 ,  B01L2200/12 ,  B01L2200/147 ,  B01L2300/0816 ,  B01L2300/1827 ,  B26D1/245 ,  B29C53/04 ,  B29C61/02 ,  B29L2009/00 ,  B32B3/28 ,  B32B7/02 ,  B32B37/144 ,  B32B38/1866 ,  B32B2307/736 ,  B44C3/04 ,  B44C3/044 ,  B44C3/087 ,  B44C5/005 ,  B44C5/06 ,  B44F1/14 ,  F28F2260/02 ,  Y10T156/1041 ,  Y10T156/1051 ,  Y10T156/1052 ,  Y10T428/2443

Abstract: The integrated device for amplification and other biological tests comprises a semiconductor material body having a surface; a plurality of buried channels extending in the semiconductor material body at a distance from the surface of the semiconductor material body; inlet and outlet ports extending from the surface of the semiconductor material body as far as the ends of the buried channels and being in fluid connection with the buried channels; and heating elements on the semiconductor material body. Temperature sensors are arranged between the heating elements above the surface of the semiconductor material body.

Abstract translation: 用于放大和其他生物测试的集成装置包括具有表面的半导体材料体; 多个掩埋沟道，其在半导体材料体的与半导体材料体的表面相距一定距离处延伸; 入口和出口从半导体材料体的表面延伸到埋入通道的端部并与埋入通道流体连接; 以及半导体材料体上的加热元件。 温度传感器布置在半导体材料体表面之上的加热元件之间。

公开(公告)号：US20020097900A1

公开(公告)日：2002-07-25

申请号：US09929833

申请日：2001-08-14

Applicant: STMicroelectronics S.r.1.

Inventor： Paolo Arena ,  Luigi Fortuna ,  Mario Lavorgna ,  Luigi Occhipinti

IPC: G06K009/00

CPC classification number: G06T7/0012 ,  G06K9/00 ,  G06T2207/30072

Abstract: The system can be used for the automatic analysis of images (I), comprising a matrix of spots, such as images of DNA microarrays after hybridisation. The system can be associatednulland preferably integrated in a single monolithic component implementing VLSI CMOS technologynullto a sensor (10) for acquiring said images (I). The system comprises a circuit (20) for processing the signals corresponding to the images (I), configured according to a cellular neural network (CNN) architecture for the parallel analogue processing of signals.

Abstract translation: 该系统可以用于图像（I）的自动分析，其包括斑点矩阵，例如杂交后的DNA微阵列的图像。 该系统可以相关联并且优选地集成在实现VLSI CMOS技术的单个单片组件中 - 用于获取所述图像（I）的传感器（10）。 该系统包括用于处理对应于根据用于信号的并行模拟处理的细胞神经网络（CNN）架构的图像（I）的信号的电路（20）。

公开(公告)号：US20150002065A1

公开(公告)日：2015-01-01

申请号：US14307643

申请日：2014-06-18

Applicant: STMICROELECTRONICS S.r.1.

Inventor： Michele Berto BOSCOLO ,  Federico MAGNI

IPC: H02P6/18

CPC classification number: H02P6/182

Abstract: A device may detect the zero-cross event of a BEMF of an electric motor with first, second, and third phase windings driven by respective first, second, and third power driving stages. The device may include a control circuit configured to place at an impedance state the third power driving stage relative to the third phase winding, the third phase winding being coupled to a zero-cross detecting circuit, introduce a masking signal to mask an output signal of the zero-cross detecting circuit in correspondence with each rising edge of a first driving signal of the first power driving stage relative to the first phase winding, and determine whether a first duty-cycle of the first driving signal is such that a duration of a masking window of the masking signal is greater than an on-time period of the first driving signal.

Abstract translation: 装置可以检测由相应的第一，第二和第三电力驱动级驱动的第一，第二和第三相绕组的电动机的BEMF的零交叉事件。 该装置可以包括控制电路，其被配置为将第三功率驱动级相对于第三相绕组处于阻抗状态，第三相绕组耦合到零交叉检测电路，引入屏蔽信号以屏蔽 所述过零检测电路对应于所述第一驱动级相对于所述第一相绕组的第一驱动信号的每个上升沿，并且确定所述第一驱动信号的第一占空比是否为 屏蔽信号的屏蔽窗口大于第一驱动信号的接通时间段。

公开(公告)号：US20020114193A1

公开(公告)日：2002-08-22

申请号：US10057767

申请日：2002-01-24

Applicant: STMicroelectronics S.r.1.

Inventor： Federico Pio

IPC: G11C011/34

CPC classification number: G11C16/16

Abstract: A method of erasing a flash memory integrated in a chip of semiconductor material and including at least one matrix of cells with a plurality of rows and a plurality of columns made in at least one insulated body, the cells of each row being connected to a corresponding word line; the method includes the step of applying a single erasing pulse relative to a selected single one of the at least one body to a selected subset of the word lines for erasing the cells of each corresponding row made in the selected body with no intermediate check of the completion of the erasure.

Abstract translation: 一种擦除集成在半导体材料芯片中的闪存的方法，包括至少一个具有至少一个绝缘体中制成的行和多个列的单元阵列，每行的单元连接到相应的 字线 该方法包括以下步骤：将相对于所选择的至少一个主体中的所选单个擦除脉冲施加到所选择的字线的子集，以擦除在所选择的主体中形成的每个对应行的单元，而不进行中间检查 完成擦除。

公开(公告)号：US20020100936A1

公开(公告)日：2002-08-01

申请号：US10061606

申请日：2002-02-01

Applicant: STMicroelectronics STMicroelectronics S.r.1.

Inventor： Ferruccio Frisina ,  Giuseppe Ferla

IPC: H01L031/119 ,  H01L031/113 ,  H01L031/062 ,  H01L029/94

CPC classification number: H01L29/7802 ,  G11C29/14 ,  G11C29/50 ,  G11C2029/0403 ,  H01L21/76202 ,  H01L21/8238 ,  H01L29/6656 ,  H01L29/66712

Abstract: Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconductor layer with an opening over the body region, polysilicon regions superimposed to the gate oxide layer, and regions of a first insulating material superimposed to the polysilicon regions. The device includes regions of a second insulating material situated on a side of both the polysilicon regions and the regions of a first insulating material and over zones of the gate oxide layer situated near the opening on the body region, oxide regions interposed between the polysilicon regions and the regions of a second insulating material, oxide spacers superimposed to the regions of a second insulating material.