公开(公告)号：US6028815A

公开(公告)日：2000-02-22

申请号：US258940

申请日：1999-03-01

申请人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich

发明人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C8/14

CPC分类号： G11C7/1006 ,  G11C8/00 ,  G11C8/14

摘要： The integrated memory has byte selection lines for selecting all the bit lines of a respective byte, as well as masking signals that are allocated to the respective byte of at least one word. In addition, the memory has a column decoder with outputs which are connected to the word selection lines, each of which, when addressed, causes all the byte selection lines for one of the words to be simultaneously selected if none of the masking signals are active. The masking signals, when activated, prevent the addressed word selection line from selecting the byte selection lines, allocated to a corresponding byte, for a corresponding word.

摘要翻译： 集成存储器具有用于选择相应字节的所有位线的字节选择线以及分配给至少一个字的相应字节的屏蔽信号。 此外，存储器具有列解码器，其具有连接到字选择线的输出，每个字选择线在寻址时都使得如果没有一个屏蔽信号有效则同时选择一个字的所有字节选择线 。 屏蔽信号被激活时，防止寻址字选择线选择分配给相应字节的字节选择线作为相应字。

公开(公告)号：US6144590A

公开(公告)日：2000-11-07

申请号：US315328

申请日：1999-05-20

申请人： Michael Markert ,  Musa Saglam ,  Sabine Schoniger ,  Peter Schrogmeier ,  Stefan Dietrich ,  Thomas Hein ,  Thilo Marx

发明人： Michael Markert ,  Musa Saglam ,  Sabine Schoniger ,  Peter Schrogmeier ,  Stefan Dietrich ,  Thomas Hein ,  Thilo Marx

IPC分类号： G11C7/18 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C7/18 ,  G11C11/4097

摘要： In a semiconductor memory, bit lines are disposed in such a way that in each case two inverted and two non-inverted bit lines lie next to one another. Adjacent switching transistors for connecting the bit lines to an inverted or a non-inverted collective line are connected to the corresponding collective line by a common contact. An advantage in terms of area is afforded by the fact that the two switching transistors have a common doping region.

摘要翻译： 在半导体存储器中，位线设置成使得在每种情况下，两个反相和两个非反相位线彼此相邻。 用于将位线连接到反相或非反相集合线的相邻开关晶体管通过公共接触连接到相应的集合线。 由于两个开关晶体管具有共同的掺杂区域，因此在面积方面具有优点。

公开(公告)号：US06101141A

公开(公告)日：2000-08-08

申请号：US344922

申请日：1999-06-28

申请人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

发明人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/02

CPC分类号： G11C7/1048 ,  G11C11/4096 ,  G11C7/1006

摘要： The integrated memory has a data line pair, which is connected to a bit line pair via at least one differential amplifier. In addition, it has a control unit for setting first potential states on the data line pair which correspond to the differential signals of data to be written to the memory cells, and for setting at least one second potential state on the data line pair which does not correspond to any datum to be written to the memory cells. Furthermore, it has a detector unit having two inputs connected to the data line pair. The detector unit initiates a specific control function when the second potential state of the data line pair occurs.

摘要翻译： 集成存储器具有数据线对，其经由至少一个差分放大器连接到位线对。 此外，它具有控制单元，用于设置数据线对上对应于要写入存储单元的数据的差分信号的第一电位状态，并且在数据线对上设置至少一个第二电位状态 不对应于要写入存储单元的任何数据。 此外，它具有检测器单元，其具有连接到数据线对的两个输入。 当发生数据线对的第二电位状态时，检测器单元启动特定的控制功能。