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    Integrated memory
    2.
    发明授权
    Integrated memory 有权
    集成内存

    公开(公告)号：US06101141A

    公开(公告)日：2000-08-08

    申请号：US344922

    申请日：1999-06-28

    申请人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    发明人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/02

    CPC分类号： G11C7/1048 ,  G11C11/4096 ,  G11C7/1006

    摘要： The integrated memory has a data line pair, which is connected to a bit line pair via at least one differential amplifier. In addition, it has a control unit for setting first potential states on the data line pair which correspond to the differential signals of data to be written to the memory cells, and for setting at least one second potential state on the data line pair which does not correspond to any datum to be written to the memory cells. Furthermore, it has a detector unit having two inputs connected to the data line pair. The detector unit initiates a specific control function when the second potential state of the data line pair occurs.

    摘要翻译： 集成存储器具有数据线对，其经由至少一个差分放大器连接到位线对。 此外，它具有控制单元，用于设置数据线对上对应于要写入存储单元的数据的差分信号的第一电位状态，并且在数据线对上设置至少一个第二电位状态 不对应于要写入存储单元的任何数据。 此外，它具有检测器单元，其具有连接到数据线对的两个输入。 当发生数据线对的第二电位状态时，检测器单元启动特定的控制功能。

    Integrated memory
    3.
    发明授权
    Integrated memory 有权
    集成内存

    公开(公告)号：US6028815A

    公开(公告)日：2000-02-22

    申请号：US258940

    申请日：1999-03-01

    申请人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich

    发明人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich

    IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C8/14

    CPC分类号： G11C7/1006 ,  G11C8/00 ,  G11C8/14

    摘要： The integrated memory has byte selection lines for selecting all the bit lines of a respective byte, as well as masking signals that are allocated to the respective byte of at least one word. In addition, the memory has a column decoder with outputs which are connected to the word selection lines, each of which, when addressed, causes all the byte selection lines for one of the words to be simultaneously selected if none of the masking signals are active. The masking signals, when activated, prevent the addressed word selection line from selecting the byte selection lines, allocated to a corresponding byte, for a corresponding word.

    摘要翻译： 集成存储器具有用于选择相应字节的所有位线的字节选择线以及分配给至少一个字的相应字节的屏蔽信号。 此外，存储器具有列解码器，其具有连接到字选择线的输出，每个字选择线在寻址时都使得如果没有一个屏蔽信号有效则同时选择一个字的所有字节选择线 。 屏蔽信号被激活时，防止寻址字选择线选择分配给相应字节的字节选择线作为相应字。

    Integrated memory having column decoder for addressing corresponding bit line
    5.
    发明授权
    Integrated memory having column decoder for addressing corresponding bit line 失效
    具有用于寻址相应位线的列解码器的集成存储器

    公开(公告)号：US06188642B1

    公开(公告)日：2001-02-13

    申请号：US09348736

    申请日：1999-07-06

    申请人： Sabine Schöniger ,  Peter Schrögmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    发明人： Sabine Schöniger ,  Peter Schrögmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    IPC分类号： G11C800

    CPC分类号： G11C8/00

    摘要： The integrated memory has a column decoder for decoding column addresses and for addressing corresponding bit lines. The memory also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder. The column decoder in each case addresses bit lines which correspond to the first and second column addresses supplied to it.

    摘要翻译： 集成存储器具有用于解码列地址并用于寻址对应位线的列解码器。 存储器还具有第一列地址总线，其用于将第一列地址传送到列解码器，以及第二列地址总线，其用于将第二列地址传送到列解码器。 列解码器在每种情况下都对应于提供给它的第一列地址和第二列地址的位线。

    Method and circuit arrangement for resetting an integrated circuit
    10.
    发明申请
    Method and circuit arrangement for resetting an integrated circuit 有权
    用于复位集成电路的方法和电路装置

    公开(公告)号：US20050253638A1

    公开(公告)日：2005-11-17

    申请号：US11117736

    申请日：2005-04-29

    申请人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schrogmeier

    发明人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schrogmeier

    IPC分类号： G06F1/24 ,  G11C5/14 ,  G11C11/4072 ,  H01L21/82 ,  H03K5/1534 ,  H03L7/00

    CPC分类号： G06F1/24 ,  H03K5/1534

    摘要： The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.

    摘要翻译： 本发明涉及一种用于复位集成电路，特别是同步半导体存储器的至少一个电路部分的方法，其中提供时钟信号和相对于后者反相的时钟信号，以便对集成电路 电路，并且当存在复位条件时，将复位信息的项目编码到时钟信号或反相时钟信号上。 本发明还涉及用于执行根据本发明的方法的电路装置，其具有时钟抑制装置和解码器电路，其用于从时钟信号或反相时钟信号中提取复位信息。