公开(公告)号：US6144590A

公开(公告)日：2000-11-07

申请号：US315328

申请日：1999-05-20

申请人： Michael Markert ,  Musa Saglam ,  Sabine Schoniger ,  Peter Schrogmeier ,  Stefan Dietrich ,  Thomas Hein ,  Thilo Marx

发明人： Michael Markert ,  Musa Saglam ,  Sabine Schoniger ,  Peter Schrogmeier ,  Stefan Dietrich ,  Thomas Hein ,  Thilo Marx

IPC分类号： G11C7/18 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C7/18 ,  G11C11/4097

摘要： In a semiconductor memory, bit lines are disposed in such a way that in each case two inverted and two non-inverted bit lines lie next to one another. Adjacent switching transistors for connecting the bit lines to an inverted or a non-inverted collective line are connected to the corresponding collective line by a common contact. An advantage in terms of area is afforded by the fact that the two switching transistors have a common doping region.

摘要翻译： 在半导体存储器中，位线设置成使得在每种情况下，两个反相和两个非反相位线彼此相邻。 用于将位线连接到反相或非反相集合线的相邻开关晶体管通过公共接触连接到相应的集合线。 由于两个开关晶体管具有共同的掺杂区域，因此在面积方面具有优点。

公开(公告)号：US06101141A

公开(公告)日：2000-08-08

申请号：US344922

申请日：1999-06-28

申请人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

发明人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/02

CPC分类号： G11C7/1048 ,  G11C11/4096 ,  G11C7/1006

摘要： The integrated memory has a data line pair, which is connected to a bit line pair via at least one differential amplifier. In addition, it has a control unit for setting first potential states on the data line pair which correspond to the differential signals of data to be written to the memory cells, and for setting at least one second potential state on the data line pair which does not correspond to any datum to be written to the memory cells. Furthermore, it has a detector unit having two inputs connected to the data line pair. The detector unit initiates a specific control function when the second potential state of the data line pair occurs.

摘要翻译： 集成存储器具有数据线对，其经由至少一个差分放大器连接到位线对。 此外，它具有控制单元，用于设置数据线对上对应于要写入存储单元的数据的差分信号的第一电位状态，并且在数据线对上设置至少一个第二电位状态 不对应于要写入存储单元的任何数据。 此外，它具有检测器单元，其具有连接到数据线对的两个输入。 当发生数据线对的第二电位状态时，检测器单元启动特定的控制功能。

公开(公告)号：US06480024B2

公开(公告)日：2002-11-12

申请号：US10046395

申请日：2001-10-19

申请人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Michael Markert ,  Thilo Marx ,  Torsten Partsch ,  Sabine Schöniger Kieser ,  Peter Schrögmeier ,  Michael Sommer ,  Christian Weis

发明人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Michael Markert ,  Thilo Marx ,  Torsten Partsch ,  Sabine Schöniger Kieser ,  Peter Schrögmeier ,  Michael Sommer ,  Christian Weis

IPC分类号： H03K190173

CPC分类号： H03K5/133 ,  H03K2005/00065 ,  H03K2005/00071 ,  H03K2005/00091

摘要： A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

公开(公告)号：US06188642B1

公开(公告)日：2001-02-13

申请号：US09348736

申请日：1999-07-06

申请人： Sabine Schöniger ,  Peter Schrögmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

发明人： Sabine Schöniger ,  Peter Schrögmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

IPC分类号： G11C800

CPC分类号： G11C8/00

摘要： The integrated memory has a column decoder for decoding column addresses and for addressing corresponding bit lines. The memory also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder. The column decoder in each case addresses bit lines which correspond to the first and second column addresses supplied to it.

摘要翻译： 集成存储器具有用于解码列地址并用于寻址对应位线的列解码器。 存储器还具有第一列地址总线，其用于将第一列地址传送到列解码器，以及第二列地址总线，其用于将第二列地址传送到列解码器。 列解码器在每种情况下都对应于提供给它的第一列地址和第二列地址的位线。

公开(公告)号：US06542389B2

公开(公告)日：2003-04-01

申请号：US10046378

申请日：2001-10-19

申请人： Stefan Dietrich ,  Patrick Heyne ,  Thilo Marx ,  Sabine Kieser ,  Michael Sommer ,  Thomas Hein ,  Michael Markert ,  Torsten Partsch ,  Peter Schrögmeier ,  Christian Weis

发明人： Stefan Dietrich ,  Patrick Heyne ,  Thilo Marx ,  Sabine Kieser ,  Michael Sommer ,  Thomas Hein ,  Michael Markert ,  Torsten Partsch ,  Peter Schrögmeier ,  Christian Weis

IPC分类号： H02M307

CPC分类号： H02M3/07

摘要： The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.

公开(公告)号：US06388944B2

公开(公告)日：2002-05-14

申请号：US09773221

申请日：2001-01-31

申请人： Peter Schrögmeier ,  Stefan Dietrich ,  Torsten Partsch ,  Thomas Hein ,  Patrick Heyne ,  Thilo Marx

发明人： Peter Schrögmeier ,  Stefan Dietrich ,  Torsten Partsch ,  Thomas Hein ,  Patrick Heyne ,  Thilo Marx

IPC分类号： G11C800

CPC分类号： G11C7/1069

摘要： A memory chip with a short data access time limits the propagation time of a bit on local data line strips which are far away from output amplifiers by centering switches with respect to a center of the cell array strips, wherein the switches are junction points between local data lines and main data lines.

摘要翻译： 具有短数据访问时间的存储器芯片通过相对于单元阵列条的中心对中开关来限制远离输出放大器的本地数据线条上的位的传播时间，其中开关是本地 数据线和主数据线。

公开(公告)号：US06670802B2

公开(公告)日：2003-12-30

申请号：US10033131

申请日：2001-10-22

申请人： Stefan Dietrich ,  Patrick Heyne ,  Thilo Marx ,  Sabine Kieser ,  Michael Sommer ,  Thomas Hein ,  Michael Markert ,  Torsten Partsch ,  Peter Schroegmeier ,  Christian Weis

发明人： Stefan Dietrich ,  Patrick Heyne ,  Thilo Marx ,  Sabine Kieser ,  Michael Sommer ,  Thomas Hein ,  Michael Markert ,  Torsten Partsch ,  Peter Schroegmeier ,  Christian Weis

IPC分类号： G01R3102

CPC分类号： G11C29/003

摘要： Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.

公开(公告)号：US06532188B2

公开(公告)日：2003-03-11

申请号：US10012161

申请日：2001-10-29

申请人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Thilo Marx ,  Torsten Partsch ,  Sabine Kieser ,  Peter Schroegmeier ,  Michael Sommer ,  Christian Weis

发明人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Thilo Marx ,  Torsten Partsch ,  Sabine Kieser ,  Peter Schroegmeier ,  Michael Sommer ,  Christian Weis

IPC分类号： G11C800

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C8/18

摘要： An integrated memory is described which has a memory cell array with column lines and row lines. A row access controller serves for activating one of the row lines and for controlling a deactivation operation. An input of a control unit is connected to a signal terminal for a signal that, in the event of a read access to one of the memory cells, defines the beginning of data outputting to a point outside the memory cell array. The data output is synchronized with a clock signal. In this case, the signal is adjustable depending on an operating frequency of the memory. An output signal of the control unit serves for triggering the deactivation operation of one of the row lines after a write access. Therefore, in the event of a write access, a comparatively high data throughput is possible even at different operating frequencies of the integrated memory.

公开(公告)号：US20060149989A1

公开(公告)日：2006-07-06

申请号：US11367218

申请日：2006-03-03

申请人： Thilo Marx ,  Peter Schrogmeier

发明人： Thilo Marx ,  Peter Schrogmeier

IPC分类号： G06F1/06

CPC分类号： G06F5/06 ,  H03K5/135 ,  H04L7/0008

摘要： An apparatus for generating a second signal having a clock based on a second clock from a first signal with a first clock comprises first and second means for sampling the first signal to determine whether the first signal has a predetermined logic state, wherein first means samples the first signal with the second clock, and second means samples the first signal with a clock phase shifted to the second clock. Means for generating the second signal generates the second signal based on the second clock if it has been determined by at least one means for sampling that the first signal has the predetermined state. Especially for time critical applications, such as a DDR-RAM, a valuable latency saving is provided by the present invention.

公开(公告)号：US06842260B2

公开(公告)日：2005-01-11

申请号：US10156538

申请日：2002-05-28

申请人： Stefan Dietrich ,  Manfred Dobler ,  Thilo Marx ,  Peter Mayer

发明人： Stefan Dietrich ,  Manfred Dobler ,  Thilo Marx ,  Peter Mayer

IPC分类号： G01B11/03 ,  G01B11/14

CPC分类号： G01B11/14

摘要： The imaging system provides assistance during the positioning of a measuring tip as it is placed onto a contact region of a microchip, in order to measure an on-chip signal. The contact region is imaged in a magnified fashion. An insertion device is provided that is suitable for providing a display of the on-chip signal in the imaging plane.

摘要翻译： 成像系统在将测量尖端放置在微芯片的接触区域上时定位时提供帮助，以便测量片上信号。 接触区域以放大的方式成像。 提供一种插入装置，其适于在成像平面中提供片上信号的显示。