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97 条记录 (耗时 0.024 秒)

    Integrated memory
    1.
    发明授权
    Integrated memory 有权
    集成内存

    公开(公告)号：US6028815A

    公开(公告)日：2000-02-22

    申请号：US258940

    申请日：1999-03-01

    申请人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich

    发明人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich

    IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C8/14

    CPC分类号： G11C7/1006 ,  G11C8/00 ,  G11C8/14

    摘要： The integrated memory has byte selection lines for selecting all the bit lines of a respective byte, as well as masking signals that are allocated to the respective byte of at least one word. In addition, the memory has a column decoder with outputs which are connected to the word selection lines, each of which, when addressed, causes all the byte selection lines for one of the words to be simultaneously selected if none of the masking signals are active. The masking signals, when activated, prevent the addressed word selection line from selecting the byte selection lines, allocated to a corresponding byte, for a corresponding word.

    摘要翻译： 集成存储器具有用于选择相应字节的所有位线的字节选择线以及分配给至少一个字的相应字节的屏蔽信号。 此外，存储器具有列解码器，其具有连接到字选择线的输出，每个字选择线在寻址时都使得如果没有一个屏蔽信号有效则同时选择一个字的所有字节选择线 。 屏蔽信号被激活时，防止寻址字选择线选择分配给相应字节的字节选择线作为相应字。

    Integrated memory
    3.
    发明授权
    Integrated memory 有权
    集成内存

    公开(公告)号：US06101141A

    公开(公告)日：2000-08-08

    申请号：US344922

    申请日：1999-06-28

    申请人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    发明人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich ,  Thilo Marx

    IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/02

    CPC分类号： G11C7/1048 ,  G11C11/4096 ,  G11C7/1006

    摘要： The integrated memory has a data line pair, which is connected to a bit line pair via at least one differential amplifier. In addition, it has a control unit for setting first potential states on the data line pair which correspond to the differential signals of data to be written to the memory cells, and for setting at least one second potential state on the data line pair which does not correspond to any datum to be written to the memory cells. Furthermore, it has a detector unit having two inputs connected to the data line pair. The detector unit initiates a specific control function when the second potential state of the data line pair occurs.

    摘要翻译： 集成存储器具有数据线对，其经由至少一个差分放大器连接到位线对。 此外，它具有控制单元，用于设置数据线对上对应于要写入存储单元的数据的差分信号的第一电位状态，并且在数据线对上设置至少一个第二电位状态 不对应于要写入存储单元的任何数据。 此外，它具有检测器单元，其具有连接到数据线对的两个输入。 当发生数据线对的第二电位状态时，检测器单元启动特定的控制功能。

    Method and circuit arrangement for resetting an integrated circuit
    4.
    发明申请
    Method and circuit arrangement for resetting an integrated circuit 有权
    用于复位集成电路的方法和电路装置

    公开(公告)号：US20050253638A1

    公开(公告)日：2005-11-17

    申请号：US11117736

    申请日：2005-04-29

    申请人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schrogmeier

    发明人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schrogmeier

    IPC分类号： G06F1/24 ,  G11C5/14 ,  G11C11/4072 ,  H01L21/82 ,  H03K5/1534 ,  H03L7/00

    CPC分类号： G06F1/24 ,  H03K5/1534

    摘要： The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.

    摘要翻译： 本发明涉及一种用于复位集成电路，特别是同步半导体存储器的至少一个电路部分的方法，其中提供时钟信号和相对于后者反相的时钟信号，以便对集成电路 电路，并且当存在复位条件时，将复位信息的项目编码到时钟信号或反相时钟信号上。 本发明还涉及用于执行根据本发明的方法的电路装置，其具有时钟抑制装置和解码器电路，其用于从时钟信号或反相时钟信号中提取复位信息。

    Parallel-serial converter
    5.
    发明授权
    Parallel-serial converter 有权
    并行串行转换器

    公开(公告)号：US07215263B2

    公开(公告)日：2007-05-08

    申请号：US11089034

    申请日：2005-03-25

    申请人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier

    发明人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier

    IPC分类号： H03M9/00

    CPC分类号： H03M9/00

    摘要： The invention relates to a parallel-serial converter for converting parallel data into serial data, in particular for or in a DDR semiconductor memory, having at least n input terminals at which n data signals are present in parallel, an output terminal for outputting a serial data signal, a controllable latch connected to the input terminals on the input side, a common storage node, which is connected to outputs of the latch and which holds a data signal of the controllable latch present last, a controllable bypass device, which has an input, which is coupled to the storage node on the output side and which has a control terminal, via which a predeterminable state present at the input of the bypass device can be switched onto the storage node. The invention furthermore relates to a semiconductor memory having such a parallel-serial converter and to a method for operating such a parallel-serial converter.

    摘要翻译： 本发明涉及一种用于将并行数据转换为串行数据的并行数据转换器，特别是用于或在DDR半导体存储器中，具有并行存在n个数据信号的至少n个输入端，用于输出串行数据的输出端子 数据信号，连接到输入侧的输入端的可控制锁存器，连接到锁存器的输出并保持最后存在的可控制锁存器的数据信号的公共存储节点，可控旁路装置，其具有 输入，其耦合到输出侧的存储节点并且具有控制终端，通过该输入可以将存在于旁路设备的输入端的可预定状态切换到存储节点。 本发明还涉及具有这种并行 - 串行转换器的半导体存储器以及用于操作这种并行 - 串行转换器的方法。

    Integrated circuit with parallel-serial converter
    6.
    发明申请
    Integrated circuit with parallel-serial converter 审中-公开
    并联串行转换器集成电路

    公开(公告)号：US20050219084A1

    公开(公告)日：2005-10-06

    申请号：US11089039

    申请日：2005-03-25

    申请人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier

    发明人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier

    IPC分类号： H03M9/00

    CPC分类号： H03M9/00

    摘要： Integrated circuit with a parallel-serial converter The invention relates to an integrated circuit and method for time-offset provision of input data for a parallel-serial converter, in particular for or in a DDR semiconductor memory, having at least n input terminals at which at least n data packets are present in parallel, a delay device arranged in a manner connected downstream of the input terminals, at least some of the data packets present on the input side being output in time-offset fashion with respect to one another by said delay device, a parallel-serial converter arranged in a manner connected downstream of the delay device, which parallel-serial converter performs a conversion of the data packets that are present in parallel and are time-offset with respect to one another into an output data signal comprising the time-offset data packets in serial form, and an output terminal for outputting the output data signal.

    摘要翻译： 具有并行串行转换器的集成电路技术领域本发明涉及一种用于时间偏移提供用于并行 - 串行转换器的输入数据的集成电路和方法，特别是用于或在DDR半导体存储器中的至少n个输入端子， 并行存在至少n个数据分组，延迟装置以连接在输入端子下游的方式布置，存在于输入侧的数据分组中的至少一些以相对于彼此的时间偏移方式通过所述 延迟装置，并联串行转换器，以与延迟装置下游相连的方式布置，该并行串行转换器对并行存在的并相对于彼此进行时间偏移的数据包进行转换，并将其转换为输出数据 包括串行形式的时间偏移数据分组的信号和用于输出输出数据信号的输出端。

    Read latency control circuit
    9.
    发明申请
    Read latency control circuit 有权
    读延迟控制电路

    公开(公告)号：US20050270852A1

    公开(公告)日：2005-12-08

    申请号：US11136712

    申请日：2005-05-25

    申请人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schroegmeier

    发明人： Stefan Dietrich ,  Thomas Hein ,  Patrick Heyne ,  Peter Schroegmeier

    IPC分类号： G06F3/06 ,  G11C7/22 ,  G11C11/4076

    CPC分类号： G11C11/4076 ,  G11C7/1066 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C2207/2272

    摘要： The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.

    摘要翻译： 本发明提供了一种用于通过用于对半导体存储器的读取访问的基于FIFO的读延迟控制电路来设置和控制读延迟（L）的方法，具有提供公共内部时钟信号的方法步骤; 从公共时钟信号产生与第一时钟信号不同的内部第一时钟信号和内部第二时钟信号; 产生用于从所述第一时钟信号读出读取数据的输出指针; 生成用于从所述第二时钟信号读取所述读取数据的输入指针; 通过在输出指针和输入指针之间分配定义的，固定地预定的时间偏移来初始化输入和输出指针。 本发明还提供了一种用于执行该方法的相应电路装置。