公开(公告)号：USD1072828S1

公开(公告)日：2025-04-29

申请号：US29826549

申请日：2022-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Gyejin Jun

公开(公告)号：US12290007B2

公开(公告)日：2025-04-29

申请号：US17966183

申请日：2022-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Siyeon Cho ,  Taeyoung Kim ,  Hyunmog Park ,  Bongyong Lee ,  Yukio Hayakawa

IPC: G11C11/15 ,  G11C11/16 ,  G11C11/18 ,  H10B61/00 ,  H10N50/85 ,  H10N52/00 ,  H10N52/80

Abstract: A magnetic memory device includes a loop-type magnetic track having a first part and a second part that are arranged in a counterclockwise direction, a first conductive line on a top surface of the first part, and a second conductive line on a bottom surface of the second part. The magnetic track includes a lower magnetic layer, a spacer layer, and an upper magnetic layer that are sequentially stacked. Each of the first and second conductive lines includes heavy metal. Each of the first and second conductive lines is configured to generate spin-orbit torque caused by current that flows therein. The spin-orbit torque causes magnetic domains in the magnetic track to move in a clockwise direction or in the counterclockwise direction.

公开(公告)号：US12289908B2

公开(公告)日：2025-04-29

申请号：US18661171

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seo Jin Jeong ,  Do Hyun Go ,  Seok Hoon Kim ,  Jung Taek Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Min-Hee Choi ,  Ryong Ha

IPC: H10D30/67 ,  H10D62/13

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

公开(公告)号：US12289683B2

公开(公告)日：2025-04-29

申请号：US18495384

申请日：2023-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Moo Lee ,  Seung Min Choi ,  Gyu Chual Kim ,  Ji Woo Lee

IPC: H04M1/725 ,  G06F1/16 ,  G06F1/3234 ,  G06F3/041 ,  G06F3/0488 ,  G06F3/04883 ,  G06F3/04886 ,  H04B17/23 ,  H04M1/02 ,  H04M1/57 ,  H04M1/724 ,  H04M19/04 ,  H04W52/02 ,  H04W68/00 ,  G06F3/0482 ,  G06F3/04847 ,  H04M1/72436 ,  H04M1/72442 ,  H04M1/72469

Abstract: An electronic device is provided. The electronic device includes a housing including a front surface and a rear surface, a display, a communication circuit, at least one processor, and a memory. The memory stores instructions which, when executed, cause the at least one processor to receive a signal from outside of the electronic device using the communication circuit, in response to receiving the signal, display a user interface on an elongated region that extends along at least one edge region of the display, and display at least one content corresponding to the signal, while displaying the user interface or after displaying the user interface.

公开(公告)号：US12289635B2

公开(公告)日：2025-04-29

申请号：US17730692

申请日：2022-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Satya Kumar Vankayala ,  Rajesh Challa ,  Pankaj Bhimrao Thorat ,  Seungil Yoon ,  Swaraj Kumar ,  Ashvin K Joseph

IPC: H04W28/02

Abstract: Embodiments herein provide a method for managing a network slice load in a wireless network. The method includes: sending, by a CN device, a request message for network slice load information to a base station of the wireless network; determining, by the base station, the network slice load based on the parameter; sending, by the base station, the response message comprising the network slice load information to the core network device for managing the network slice load; determining, by a CN device, the network slice load at the base station based on the response message; and managing, by a CN device, the network slice load at the base station.

公开(公告)号：US12289620B2

公开(公告)日：2025-04-29

申请号：US17871442

申请日：2022-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Satya Kumar Vankayala ,  Ashvin Kaithara Joseph ,  Seungil Yoon

IPC: H04W24/02 ,  H04L41/147 ,  H04W24/08 ,  H04W36/00

Abstract: A method of enabling multi-connectivity in a wireless network includes predicting at least one of a RLF, a call drop, and a jitter based on a plurality of Key Performance Indicators (KPIs) associated with the UE and the wireless network, determining whether the UE is in one of a Dual Connectivity (DC) mode and a carrier aggregation (CA) mode, performing one of: adding a new secondary gNodeB (gNB) in response to determining that the UE is not in both the DC mode and the CA mode and converting the new gNB to a master gNB, converting an existing secondary gNodeB to a master gNodeB with one of an existing Master Cell Group (MCG) gNodeB and another gNodeB as the secondary gNodeB, in response to determining that the UE is in the DC mode, and converting an existing secondary cell to a primary cell.

公开(公告)号：US12289557B2

公开(公告)日：2025-04-29

申请号：US18329322

申请日：2023-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon Jun

IPC: H04N25/78 ,  H03G3/00 ,  H03M1/12 ,  H03M1/18 ,  H04N25/709

Abstract: Disclosed is an amplifier circuit including a first input terminal that receives a ramp signal, a second input terminal that receives a pixel signal, an output terminal that outputs an output signal, wherein the output signal is based on comparing the pixel signal and the ramp signal, a capacitor that is electrically connected between the output terminal and a ground terminal, a switch that is electrically connected with the capacitor, and a current source that outputs a power current. The pixel signal corresponds to a first conversion gain or a second conversion gain, and a value of the second conversion gain is higher than a value of the first conversion gain, and a bandwidth of the amplifier circuit is adjusted depending on whether the pixel signal corresponds to the first conversion gain or the second conversion gain.

公开(公告)号：US12289537B2

公开(公告)日：2025-04-29

申请号：US18323500

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Manish Goel ,  Girish Kalyanasundaram ,  Puneet Pandey ,  Manjit Hota

IPC: H04N23/80 ,  H04N25/46 ,  H04N25/74

Abstract: A method of performing image signal processing includes: determining whether at least one neighbor pixel is available for each of a plurality of current pixels in a current block, wherein each of the plurality of current pixels has a current pixel value; estimating a predict pixel value for each of the plurality of current pixels in the current block based on a pixel value of the at least one neighbor pixel corresponding to each of the plurality of current pixels, using at least one of a plurality of predefined prediction modes; determining a difference metric between the predict pixel value and the current pixel value for each of the plurality of current pixels; and obtaining a processed pixel value for each of the plurality of current pixels based on the difference metric.

公开(公告)号：US12289105B2

公开(公告)日：2025-04-29

申请号：US18514975

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngho Choi ,  Donghyuk Lim ,  Kibaek Kwon

IPC: H03K21/00 ,  H03K5/13 ,  H03K5/24 ,  H03K19/21

Abstract: An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

公开(公告)号：US12288991B2

公开(公告)日：2025-04-29

申请号：US17751105

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkyung Jang ,  Kawon Cheon ,  Jaeseok Park ,  Jaehyun Park ,  Joayoung Lee ,  Hoon Han

IPC: H02J50/00 ,  H02J7/00 ,  H02J50/12 ,  H02J50/80 ,  H02J50/90

Abstract: A wireless power receiving device includes a first housing, a second housing coupled to the first housing to be changed in relative position with respect to the first housing, a first resonance circuit disposed in the first housing, and at least one processor. The at least one processor may be configured to control the wireless power receiving device to wirelessly receive power from a wireless power transmitting device through the first resonance circuit, identify a charging efficiency corresponding to the received wireless power, and in case the identified charging efficiency is less than a threshold, provide content for changing an angle between the first housing and the second housing.