公开(公告)号：US20130113102A1

公开(公告)日：2013-05-09

申请号：US13291470

申请日：2011-11-08

申请人： Junjing Bao ,  Shaoning Yao ,  Xuesong Li ,  Samuel S. S. Choi

发明人： Junjing Bao ,  Shaoning Yao ,  Xuesong Li ,  Samuel S. S. Choi

IPC分类号： H01L23/538 ,  H01L21/768 ,  B82Y30/00 ,  B82Y40/00

CPC分类号： H01L23/4827 ,  B82Y40/00 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/481 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

公开(公告)号：US07790601B1

公开(公告)日：2010-09-07

申请号：US12561651

申请日：2009-09-17

申请人： Samuel S. S. Choi ,  Lawrence A. Clevenger ,  Maxime Darnon ,  Daniel C. Edelstein ,  Satyanarayana Venkata Nitta ,  Shom Ponoth ,  Pak Leung

发明人： Samuel S. S. Choi ,  Lawrence A. Clevenger ,  Maxime Darnon ,  Daniel C. Edelstein ,  Satyanarayana Venkata Nitta ,  Shom Ponoth ,  Pak Leung

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/31111 ,  H01L21/31144

摘要： Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.

摘要翻译： 公开了一种在互连中形成气隙的积分方法的过程。 在半导体衬底上的金属布线层的顶部上沉积介电覆盖层，接着是牺牲介电层和图案转移层。 图案通过图案转移层，牺牲介电层，电介质盖层转移到金属布线层中。 牺牲介电层的存在有助于控制电介质盖层的厚度和轮廓，这进而影响互连的可靠性。

公开(公告)号：US09324634B2

公开(公告)日：2016-04-26

申请号：US13291470

申请日：2011-11-08

申请人： Junjing Bao ,  Shaoning Yao ,  Xuesong Li ,  Samuel S. S. Choi

发明人： Junjing Bao ,  Shaoning Yao ,  Xuesong Li ,  Samuel S. S. Choi

IPC分类号： H01L23/482 ,  H01L23/532 ,  H01L21/768 ,  H01L23/48 ,  B82Y40/00

CPC分类号： H01L23/4827 ,  B82Y40/00 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/481 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

摘要翻译： 一种用于制造具有增强的性能和可靠性的互连结构的互连结构和方法，所述互连结构和方法通过利用基于石墨烯的阻挡金属层来阻挡从电介质层渗入互连结构中的氧，并阻止从互连结构到电介质层的铜扩散， 被披露。 在电介质层中形成至少一个开口。 形成设置在电介质层上的基于石墨烯的阻挡金属层。 形成设置在石墨烯阻挡金属层上的种子层。 形成设置在种子层上的电镀铜层。 形成平坦化表面，其中除去石墨烯基阻挡金属层，籽晶层和电镀铜层的一部分。 此外，形成设置在平坦化表面上的覆盖层。