公开(公告)号：US07790601B1

公开(公告)日：2010-09-07

申请号：US12561651

申请日：2009-09-17

申请人： Samuel S. S. Choi ,  Lawrence A. Clevenger ,  Maxime Darnon ,  Daniel C. Edelstein ,  Satyanarayana Venkata Nitta ,  Shom Ponoth ,  Pak Leung

发明人： Samuel S. S. Choi ,  Lawrence A. Clevenger ,  Maxime Darnon ,  Daniel C. Edelstein ,  Satyanarayana Venkata Nitta ,  Shom Ponoth ,  Pak Leung

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/31111 ,  H01L21/31144

摘要： Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.

摘要翻译： 公开了一种在互连中形成气隙的积分方法的过程。 在半导体衬底上的金属布线层的顶部上沉积介电覆盖层，接着是牺牲介电层和图案转移层。 图案通过图案转移层，牺牲介电层，电介质盖层转移到金属布线层中。 牺牲介电层的存在有助于控制电介质盖层的厚度和轮廓，这进而影响互连的可靠性。

公开(公告)号：US20080265377A1

公开(公告)日：2008-10-30

申请号：US11741908

申请日：2007-04-30

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Ponoth ,  Gregory Breyta

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Ponoth ,  Gregory Breyta

IPC分类号： H01L21/311 ,  H01L29/06

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming cavities within a semiconductor device is disclosed. The method comprises depositing an anti-nucleating layer on the interior surface of cavities within an ILD layer of the semiconductor device. This anti-nucleating layer prevents subsequently deposited dielectric layers from forming within the cavities. By preventing the formation of these layers, the capacitance is reduced, thereby resulting in improved semiconductor performance.

摘要翻译： 公开了一种在半导体器件内形成空腔的方法。 该方法包括在半导体器件的ILD层内的空腔的内表面上沉积抗成核层。 该抗成核层防止随后沉积的介电层在空腔内形成。 通过防止这些层的形成，电容减小，从而提高半导体性能。

公开(公告)号：US08896120B2

公开(公告)日：2014-11-25

申请号：US12768267

申请日：2010-04-27

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/02 ,  H01L21/31 ,  H01L21/027 ,  H01L23/522

CPC分类号： H01L21/76829 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/0276 ,  H01L21/31 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地，本文所述的方法提供了内置于可光图案化的低k材料中的互连结构，其中不同深度的气隙通过光刻图案中的低k材料中的光刻来定义。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US20110260326A1

公开(公告)日：2011-10-27

申请号：US12768267

申请日：2010-04-27

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76829 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/0276 ,  H01L21/31 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地，本文所述的方法提供了内置于可光图案化的低k材料中的互连结构，其中不同深度的气隙通过光刻图案中的低k材料中的光刻来定义。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US20110221062A1

公开(公告)日：2011-09-15

申请号：US12721032

申请日：2010-03-10

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Satyanarayana V. Nitta ,  Anthony D. Lisi ,  Qinghuang Lin

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Satyanarayana V. Nitta ,  Anthony D. Lisi ,  Qinghuang Lin

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/4821 ,  C08L83/04 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地说，本文描述的方法提供内置于光可图案化的低k材料中的互连结构，其中通过光刻法在光可图案化的低k材料中限定气隙。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US08642252B2

公开(公告)日：2014-02-04

申请号：US12721032

申请日：2010-03-10

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Satyanarayana V. Nitta ,  Anthony D. Lisi ,  Qinghuang Lin

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Satyanarayana V. Nitta ,  Anthony D. Lisi ,  Qinghuang Lin

IPC分类号： H01L21/764

CPC分类号： H01L23/4821 ,  C08L83/04 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地说，本文描述的方法提供内置于光可图案化的低k材料中的互连结构，其中通过光刻法在光可图案化的低k材料中限定气隙。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US20120280398A1

公开(公告)日：2012-11-08

申请号：US13540931

申请日：2012-07-03

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

IPC分类号： H01L23/522

CPC分类号： H01L23/53295 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5222 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地说，本文描述的方法提供内置于光可图案化的低k材料中的互连结构，其中通过光刻法在光可图案化的低k材料中限定气隙。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US08183694B2

公开(公告)日：2012-05-22

申请号：US13021774

申请日：2011-02-06

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Anthony D. Lisi ,  Satya V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Anthony D. Lisi ,  Satya V. Nitta

IPC分类号： H01L29/40

CPC分类号： H01L21/31144 ,  H01L21/7682

摘要： A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.

摘要翻译： 在具有电介质层的基板上产生气隙的方法包括通过需要气隙的光刻来定义线。 线的尺寸通过修整工艺（各向同性蚀刻）收缩。 图案的色调通过施加被向下蚀刻到图案的顶部的平坦化层来反转。 去除光致抗蚀剂，导致亚光刻沟槽，其转移到盖层中，最终转移到两条金属线之间的电介质中。 暴露的电介质最终被损坏，并被蚀刻掉，导致金属线之间的气隙。 间隙通过在随后的电介质的沉积期间发生的夹断来密封。

公开(公告)号：US20110272810A1

公开(公告)日：2011-11-10

申请号：US12776885

申请日：2010-05-10

申请人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

发明人： Lawrence A. Clevenger ,  Maxime Darnon ,  Qinghuang Lin ,  Anthony D. Lisi ,  Satyanarayana V. Nitta

IPC分类号： H01L23/522 ,  G03F7/20

CPC分类号： H01L23/53295 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5222 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

摘要翻译： 公开了使用可光图案化的低k材料制造用于VLSI和ULSI器件的含气隙的金属 - 绝缘体互连结构的方法以及形成的含气隙的互连结构。 更具体地说，本文描述的方法提供内置于光可图案化的低k材料中的互连结构，其中通过光刻法在光可图案化的低k材料中限定气隙。 在本发明的方法中，不需要蚀刻步骤来形成气隙。 由于在形成可光图案化的低k材料内的气隙中不需要蚀刻步骤，所以本发明公开的方法提供了高度可靠的互连结构。

公开(公告)号：US08809183B2

公开(公告)日：2014-08-19

申请号：US12887010

申请日：2010-09-21

申请人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76861 ,  H01L21/76862 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

摘要翻译： 选择性导电盖通过对金属互连结构的暴露的下面的电介质表面可选择的化学镀层沉积在金属线的暴露的金属表面上。 介电材料层沉积在选择性导电盖和暴露的下面的介质层上，而不需要预清洗。 介电材料层被平坦化以形成与选择性导电帽的最顶面共面的水平平面。 执行预清洁，并且在选择性导电盖和介电材料层的平坦化表面上沉积电介质盖层。 由于包括由预清洗层损坏的表面的界面垂直偏离金属线的最上表面，所以金属线中的金属沿着界面的电迁移减少或消除。