公开(公告)号：US07790601B1

公开(公告)日：2010-09-07

申请号：US12561651

申请日：2009-09-17

申请人： Samuel S. S. Choi ,  Lawrence A. Clevenger ,  Maxime Darnon ,  Daniel C. Edelstein ,  Satyanarayana Venkata Nitta ,  Shom Ponoth ,  Pak Leung

发明人： Samuel S. S. Choi ,  Lawrence A. Clevenger ,  Maxime Darnon ,  Daniel C. Edelstein ,  Satyanarayana Venkata Nitta ,  Shom Ponoth ,  Pak Leung

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/31111 ,  H01L21/31144

摘要： Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a sacrificial dielectric layer and pattern transfer layers. A pattern is transferred through the pattern transfer layers, sacrificial dielectric layer, dielectric cap layer and into the metal wiring layer. The presence of the sacrificial dielectric layer aids in controlling the thickness and profile of the dielectric cap layer which in turn affects reliability of the interconnect.

摘要翻译： 公开了一种在互连中形成气隙的积分方法的过程。 在半导体衬底上的金属布线层的顶部上沉积介电覆盖层，接着是牺牲介电层和图案转移层。 图案通过图案转移层，牺牲介电层，电介质盖层转移到金属布线层中。 牺牲介电层的存在有助于控制电介质盖层的厚度和轮廓，这进而影响互连的可靠性。

公开(公告)号：US20110163446A1

公开(公告)日：2011-07-07

申请号：US12983885

申请日：2011-01-04

申请人： Satyanarayana Venkata Nitta ,  Sampath PURUSHOTHAMAN ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Ponoth

发明人： Satyanarayana Venkata Nitta ,  Sampath PURUSHOTHAMAN ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Ponoth

IPC分类号： H01L23/48

CPC分类号： H01L21/7682

摘要： A structure and method to produce an airgap on a substrate having a dielectric layer and copper interconnects with sublithographic perforations therein which are ordered throughout the wafer structure in a macro level and a micro level with no change in order orientation and the top layer of the copper interconnects are not exposed.

摘要翻译： 在具有电介质层和铜互连的衬底上产生气隙的结构和方法，其中的亚光刻穿孔在整个晶片结构中以宏观水平和微观级别排列，并且铜层的顶层 互连不暴露。

公开(公告)号：US20080265377A1

公开(公告)日：2008-10-30

申请号：US11741908

申请日：2007-04-30

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Ponoth ,  Gregory Breyta

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Ponoth ,  Gregory Breyta

IPC分类号： H01L21/311 ,  H01L29/06

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming cavities within a semiconductor device is disclosed. The method comprises depositing an anti-nucleating layer on the interior surface of cavities within an ILD layer of the semiconductor device. This anti-nucleating layer prevents subsequently deposited dielectric layers from forming within the cavities. By preventing the formation of these layers, the capacitance is reduced, thereby resulting in improved semiconductor performance.

摘要翻译： 公开了一种在半导体器件内形成空腔的方法。 该方法包括在半导体器件的ILD层内的空腔的内表面上沉积抗成核层。 该抗成核层防止随后沉积的介电层在空腔内形成。 通过防止这些层的形成，电容减小，从而提高半导体性能。

公开(公告)号：US08809183B2

公开(公告)日：2014-08-19

申请号：US12887010

申请日：2010-09-21

申请人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76861 ,  H01L21/76862 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

摘要翻译： 选择性导电盖通过对金属互连结构的暴露的下面的电介质表面可选择的化学镀层沉积在金属线的暴露的金属表面上。 介电材料层沉积在选择性导电盖和暴露的下面的介质层上，而不需要预清洗。 介电材料层被平坦化以形成与选择性导电帽的最顶面共面的水平平面。 执行预清洁，并且在选择性导电盖和介电材料层的平坦化表面上沉积电介质盖层。 由于包括由预清洗层损坏的表面的界面垂直偏离金属线的最上表面，所以金属线中的金属沿着界面的电迁移减少或消除。

公开(公告)号：US09105693B2

公开(公告)日：2015-08-11

申请号：US13614563

申请日：2012-09-13

申请人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

发明人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L29/40 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

摘要翻译： 微电子结构和微电子结构的制造方法提供插入在多个导体层之间的多个空隙。 多个空隙也位于衬垫层和层间电介质层之间。 空隙提供了微电子结构的增强的电性能。

公开(公告)号：US08120179B2

公开(公告)日：2012-02-21

申请号：US12615354

申请日：2009-11-10

申请人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

发明人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

摘要翻译： 金属互连结构包括至少一对金属线，它们之间的腔，以及位于腔的至少一部分壁上的介电金属扩散阻挡层。 在一对金属线之间形成空腔之后，在空腔的暴露表面上形成介电金属扩散阻挡层。 在一对金属线之上形成介电材料层以封装空腔。 电介质金属扩散阻挡层防止金属和杂质从一个金属线扩散到另一个金属线，反之亦然，从而防止一对金属线之间的电短路。

公开(公告)号：US07943480B2

公开(公告)日：2011-05-17

申请号：US12029800

申请日：2008-02-12

申请人： Daniel C. Edelstein ,  Nicholas C. M. Fuller ,  David V. Horak ,  Elbert E. Huang ,  Wai-Kin Li ,  Anthony D. Lisi ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Daniel C. Edelstein ,  Nicholas C. M. Fuller ,  David V. Horak ,  Elbert E. Huang ,  Wai-Kin Li ,  Anthony D. Lisi ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/00

CPC分类号： H01L21/7682 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

摘要： Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.

摘要翻译： 公开了亚光刻尺寸气隙形成和相关结构。 在一个实施例中，一种方法包括在衬底上形成包括互连的介质层; 在电介质层上沉积盖层; 在所述盖层上沉积光致抗蚀剂; 图案化光致抗蚀剂以包括最多部分地覆盖互连的第一沟槽图案; 在所述第一沟槽图案内形成间隔物以形成具有亚光刻尺寸的第二沟槽图案; 将所述第二沟槽图案转移到所述覆盖层中并进入所述互连之间的所述介电层; 并且通过夹住介电层中的沟槽而沉积另一介质层以形成气隙。

公开(公告)号：US20120068344A1

公开(公告)日：2012-03-22

申请号：US12887010

申请日：2010-09-21

申请人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5329 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76861 ,  H01L21/76862 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

摘要翻译： 选择性导电盖通过对金属互连结构的暴露的下面的电介质表面可选择的化学镀层沉积在金属线的暴露的金属表面上。 介电材料层沉积在选择性导电盖和暴露的下面的介质层上，而不需要预清洗。 介电材料层被平坦化以形成与选择性导电帽的最顶面共面的水平平面。 执行预清洁，并且在选择性导电盖和介电材料层的平坦化表面上沉积电介质盖层。 由于包括由预清洗层损坏的表面的界面垂直偏离金属线的最上表面，所以金属线中的金属沿着界面的电迁移减少或消除。

公开(公告)号：US20100210098A1

公开(公告)日：2010-08-19

申请号：US12372174

申请日：2009-02-17

申请人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

发明人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

IPC分类号： H01L21/283

CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76829

摘要： A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer.

摘要翻译： 一种形成用于半导体器件的触点的方法，所述方法包括在多个栅极叠层之间沉积层间电介质（ILD），其中层间电介质层内的阴影由栅极堆叠之间的空间限定，填充 具有初始填充材料的图案，在栅极堆叠上的电介质上沉积掩模材料，并且选择性地蚀刻填充材料以形成接触孔。 填充材料可以是自组装材料，例如多嵌段共聚物，其中嵌段自由地在密封区内垂直组织，使得嵌段材料的选择性蚀刻将从竖纹中去除垂直组织的块，而是离开 在门区域上至少有一个块。 在另一个实施方案中，填充材料可以是金属，掩蔽材料可以是聚对二甲苯基聚合物。

公开(公告)号：US07888252B2

公开(公告)日：2011-02-15

申请号：US12372174

申请日：2009-02-17

申请人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

发明人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76829

摘要： A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer.

摘要翻译： 一种形成用于半导体器件的触点的方法，所述方法包括在多个栅极叠层之间沉积层间电介质（ILD），其中层间电介质层内的阴影由栅极堆叠之间的空间限定，填充 具有初始填充材料的图案，在栅极堆叠上的电介质上沉积掩模材料，并且选择性地蚀刻填充材料以形成接触孔。 填充材料可以是自组装材料，例如多嵌段共聚物，其中嵌段自由地在密封区内垂直组织，使得嵌段材料的选择性蚀刻将从竖纹中去除垂直组织的块，而是离开 在门区域上至少有一个块。 在另一个实施方案中，填充材料可以是金属，掩蔽材料可以是聚对二甲苯基聚合物。