公开(公告)号：US07057217B2

公开(公告)日：2006-06-06

申请号：US10672035

申请日：2003-09-26

申请人： Sang-Seok Kang ,  Jong-Hyun Choi ,  Sang-Ki Hwang

发明人： Sang-Seok Kang ,  Jong-Hyun Choi ,  Sang-Ki Hwang

IPC分类号： H01L27/10

CPC分类号： G11C17/143 ,  G11C29/785 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse circuit according to the present invention includes first and second fuses, each of which has a first end and a second end. The first and second ends of the first fuse are connected in a straight line. The first end of the second fuse is spaced by a first interval from the first end of the first fuse, and the second end thereof is spaced by a second interval from the second end of the first fuse. The first ends of the first and second fuses have the same widths as those of the second ends thereof. Alternatively, the first ends of the first and second fuses have narrower widths that those of the second ends thereof.

摘要翻译： 根据本发明的熔丝电路包括第一和第二熔丝，每个熔丝具有第一端和第二端。 第一保险丝的第一端和第二端以直线连接。 第二保险丝的第一端与第一保险丝的第一端隔开第一间隔，并且第二保险丝的第二端与第一保险丝的第二端隔开第二间隔。 第一和第二熔断器的第一端具有与其第二端相同的宽度。 或者，第一和第二熔断器的第一端的宽度比第二端的宽度窄。

公开(公告)号：US06650567B1

公开(公告)日：2003-11-18

申请号：US08213004

申请日：1994-03-14

申请人： Sung-Hee Cho ,  Sang-Ki Hwang ,  Hyong-Gon Lee

发明人： Sung-Hee Cho ,  Sang-Ki Hwang ,  Hyong-Gon Lee

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C17/123

摘要： A nonvolatile semiconductor integrated circuit having a cell array consisting of a plurality of memory strings each having first to N-th (N=2, 3, 4, . . . ) memory cell transistors of a NAND structure includes a plurality of first string select transistors connected in series to the first memory cell transistor, and a plurality of second string select transistors connected in series to the N-th memory cell transistor. One of the string select transistors serially connected to the first and N-th memory cell transistors has a control terminal connected to a ground connecting point, thus to have a ground select function as well as a string select function.

摘要翻译： 具有由NAND结构的第一至第N（N = 2,3,4 ...）个存储单元晶体管组成的多个存储串组成的单元阵列的非易失性半导体集成电路包括多个第一串选择 与第一存储单元晶体管串联连接的晶体管，以及与第N个存储单元晶体管串联连接的多个第二串选择晶体管。 串联连接到第一和第N存储单元晶体管的串选择晶体管之一具有连接到接地连接点的控制端子，从而具有接地选择功能以及串选择功能。

公开(公告)号：US07843720B2

公开(公告)日：2010-11-30

申请号：US12256564

申请日：2008-10-23

申请人： Hye-jin Kim ,  Sang-ki Hwang

发明人： Hye-jin Kim ,  Sang-ki Hwang

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C2213/72 ,  G11C2213/79

摘要： Disclosed are a phase change memory device in which an active time is reduced and a method of discharging a bitline in the phase change memory device. In the phase change memory device having the reduced active time and the method of discharging the bitline in the phase change memory device, the bitline is either always discharged when the phase change memory device is in standby, is discharged after the active operation of the phase change memory device, or is discharged prior to and after the active operation of the phase change memory device.

摘要翻译： 公开了其中有效时间减少的相变存储器件以及在相变存储器件中放电位线的方法。 在相变存储器件中具有减小的有效时间的相变存储器件和放电位线的方法中，当相变存储器件处于待机状态时，位线或者总是被放电，在相位的有效操作之后被放电 更换存储器件，或在相变存储器件的有效操作之前和之后被放电。

公开(公告)号：US5995422A

公开(公告)日：1999-11-30

申请号：US544439

申请日：1995-11-17

申请人： Heung-Soo Im ,  Sang-Ki Hwang ,  Hyong-Gon Lee

发明人： Heung-Soo Im ,  Sang-Ki Hwang ,  Hyong-Gon Lee

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/84

摘要： The present invention provides a redundancy circuit in a semiconductor memory device which has spare memory cells which can store information that can be substituted for data of defective memory cells after the completion of the manufacturing process. If addresses designating the defective memory cells are externally input, the redundancy circuit generates a defective cell relief address signal which corresponds to the address designating the defective memory cell and is used to prevent defective data stored in normal memory cells from being output and causes correction data, to be substituted for the defective data output in correspondence with the defective cell relief address.

摘要翻译： 本发明提供一种半导体存储器件中的冗余电路，该冗余电路具有备用存储器单元，其可以存储在制造过程完成之后可以代替有缺陷的存储器单元的数据的信息。 如果指定缺陷存储单元的地址是外部输入的，则冗余电路产生与指定有缺陷存储单元的地址对应的有缺陷的单元释放地址信号，并且用于防止存储在正常存储单元中的故障数据被输出并导致校正数据 ，以代替与有缺陷的单元缓冲地址对应的缺陷数据输出。

公开(公告)号：US5528537A

公开(公告)日：1996-06-18

申请号：US505038

申请日：1995-07-21

申请人： Hyong-Gon Lee ,  Sang-Ki Hwang ,  Cheol-Ung Jang ,  Young-Wi Ko ,  Sung-Hee Cho

发明人： Hyong-Gon Lee ,  Sang-Ki Hwang ,  Cheol-Ung Jang ,  Young-Wi Ko ,  Sung-Hee Cho

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C17/12 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/115 ,  G11C17/123 ,  H01L27/112

摘要： A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.

摘要翻译： 具有适用于高速运行和低电源电压的单元结构的非易失性半导体存储器。 非易失性半导体存储器包括切换电路，其包括通过其相应端子连接到相应位线的块选择晶体管。 该切换电路仅在选择与开关电路对应的串时发送信号。 在构成存储晶体管的源区和漏区的第一有源区具有不同杂质浓度的第二有源区形成在连接存储器串和位线的位线接触部的衬底接触部分。 第二有源区的杂质浓度低于第一有源区的杂质浓度。

公开(公告)号：US20090097307A1

公开(公告)日：2009-04-16

申请号：US12285657

申请日：2008-10-10

申请人： Joon-min Park ,  Young-kug Moon ,  Sang-ki Hwang

发明人： Joon-min Park ,  Young-kug Moon ,  Sang-ki Hwang

IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C7/06

CPC分类号： G11C7/18 ,  G11C7/08 ,  G11C13/0004 ,  G11C2213/72

摘要： A phase-change random access memory (PRAM) device includes a PRAM cell array having a first bank that includes first to mth sectors, where m is a positive integer of at least 2, and sense amplifiers disposed between an xth sector and an (x+1)th sector of the bank, where x is a positive integer less than m.

摘要翻译： 相变随机存取存储器（PRAM）器件包括具有包括第一至第m个扇区的第一存储体的PRAM单元阵列，其中m是至少为2的正整数，以及设置在第x个扇区和（x +1）行，其中x是小于m的正整数。

公开(公告)号：USRE36490E

公开(公告)日：2000-01-11

申请号：US886107

申请日：1997-06-30

申请人： Sang Ki Hwang ,  Tae Sung Jung ,  Kyu Hyun Choi

发明人： Sang Ki Hwang ,  Tae Sung Jung ,  Kyu Hyun Choi

IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C5/14 ,  G11C11/34 ,  G11C11/401 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G11C13/00

CPC分类号： G11C5/025 ,  G11C5/14

摘要： A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is positioned adjacent a ground line, which is positioned adjacent another power line and so on. Signal lines carrying signals to and from the circuitry are also formed directly above memory cell arrays.

摘要翻译： 具有位于存储单元阵列之间的电路的存储单元器件包括到存储单元阵列正上方形成的电路的电源和地线。 电源线和接地线平行并且位于相邻的交替图案中，使得电力线位于邻近另一电力线等的接地线附近。 在电路上传送信号的信号线也直接形成在存储单元阵列上方。

公开(公告)号：US20090129144A1

公开(公告)日：2009-05-21

申请号：US12256564

申请日：2008-10-23

申请人： Hye-jin KIM ,  Sang-ki HWANG

发明人： Hye-jin KIM ,  Sang-ki HWANG

IPC分类号： G11C11/00 ,  G11C8/08 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C2213/72 ,  G11C2213/79

摘要： Disclosed are a phase change memory device in which an active time is reduced and a method of discharging a bitline in the phase change memory device. In the phase change memory device having the reduced active time and the method of discharging the bitline in the phase change memory device, the bitline is either always discharged when the phase change memory device is in standby, is discharged after the active operation of the phase change memory device, or is discharged prior to and after the active operation of the phase change memory device.

摘要翻译： 公开了其中有效时间减少的相变存储器件以及在相变存储器件中放电位线的方法。 在相变存储器件中具有减小的有效时间的相变存储器件和放电位线的方法中，当相变存储器件处于待机状态时，位线或者总是被放电，在相位的有效操作之后被放电 更换存储器件，或在相变存储器件的有效操作之前和之后被放电。

公开(公告)号：US07142045B2

公开(公告)日：2006-11-28

申请号：US10881937

申请日：2004-06-30

申请人： Hyun-Sun Mo ,  Sang-Ki Hwang

发明人： Hyun-Sun Mo ,  Sang-Ki Hwang

IPC分类号： G05F3/02

CPC分类号： G11C5/147

摘要： There is provided an internal voltage generating circuit that reliably supplies a constant internal voltage to the interior of a semiconductor device without regard to an external voltage, where the internal voltage generating circuit compares a first reference voltage with a first internal voltage fed back to generate the first internal voltage following the first reference voltage, receives the first internal voltage to generate a second reference voltage which is more insensitive to fluctuation of the external voltage than the first reference voltage, and compares the second reference voltage with a second internal voltage fed back to generate the second internal voltage which follows the second reference voltage and has a variation gradient smaller than that of the first internal voltage when the external voltage is changed, thereby supplying the second internal voltage to a circuit requiring stabilized internal voltage, which is obtained to increase stability and durability of the operation of the semiconductor device.

摘要翻译： 提供内部电压发生电路，其可靠地将外部电压与内部电压产生电路进行比较，将第一参考电压与反馈的第一内部电压进行比较，从而可靠地将恒定的内部电压提供给半导体器件的内部， 第一内部电压跟随第一参考电压，接收第一内部电压以产生比第一参考电压对外部电压的波动更不敏感的第二参考电压，并将第二参考电压与反馈到第二参考电压的第二内部电压进行比较 产生跟随第二参考电压的第二内部电压，并且当外部电压改变时具有小于第一内部电压的变化梯度的变化梯度，从而将第二内部电压提供给需要稳定的内部电压的电路，从而增加 稳定性和耐久性 半导体器件的操作。

公开(公告)号：US20050017704A1

公开(公告)日：2005-01-27

申请号：US10881937

申请日：2004-06-30

申请人： Hyun-Sun Mo ,  Sang-Ki Hwang

发明人： Hyun-Sun Mo ,  Sang-Ki Hwang

IPC分类号： G11C5/14 ,  G11C5/00

CPC分类号： G11C5/147

摘要： There is provided an internal voltage generating circuit that reliably supplies a constant internal voltage to the interior of a semiconductor device without regard to an external voltage, where the internal voltage generating circuit compares a first reference voltage with a first internal voltage fed back to generate the first internal voltage following the first reference voltage, receives the first internal voltage to generate a second reference voltage which is more insensitive to fluctuation of the external voltage than the first reference voltage, and compares the second reference voltage with a second internal voltage fed back to generate the second internal voltage which follows the second reference voltage and has a variation gradient smaller than that of the first internal voltage when the external voltage is changed, thereby supplying the second internal voltage to a circuit requiring stabilized internal voltage, which is obtained to increase stability and durability of the operation of the semiconductor device.

摘要翻译： 提供内部电压发生电路，其可靠地将外部电压与内部电压产生电路进行比较，将第一参考电压与反馈的第一内部电压进行比较，从而可靠地将恒定的内部电压提供给半导体器件的内部， 第一内部电压跟随第一参考电压，接收第一内部电压以产生比第一参考电压对外部电压的波动更不敏感的第二参考电压，并将第二参考电压与反馈到第二参考电压的第二内部电压进行比较 产生跟随第二参考电压的第二内部电压，并且当外部电压改变时具有小于第一内部电压的变化梯度的变化梯度，从而将第二内部电压提供给需要稳定的内部电压的电路，从而增加 稳定性和耐久性 半导体器件的操作。