公开(公告)号：US06888733B2

公开(公告)日：2005-05-03

申请号：US10618206

申请日：2003-07-09

申请人： Cheol-Ung Jang ,  Young-Joon Choi

发明人： Cheol-Ung Jang ,  Young-Joon Choi

IPC分类号： G06F12/06 ,  G11C16/00 ,  G11C16/20 ,  G11C5/02

CPC分类号： G11C16/20 ,  G11C2029/4402

摘要： A multiple chip memory system capable of providing state information relating to each chip embedded therein. The multiple chip memory system includes a first chip enabled by a first chip selection signal, and informing of a self state by a first ready/busy signal; and a second chip enabled by a second chip selection signal, and informing of a self state by a second ready/busy signal.

摘要翻译： 一种能够提供与嵌入其中的每个芯片相关的状态信息的多芯片存储器系统。 多芯片存储器系统包括由第一芯片选择信号使能的第一芯片，以及通过第一就绪/忙信号通知自身状态; 以及由第二芯片选择信号使能的第二芯片，并且通过第二就绪/忙信号通知自身状态。

公开(公告)号：US5886937A

公开(公告)日：1999-03-23

申请号：US1936

申请日：1997-12-31

申请人： Cheol-Ung Jang

发明人： Cheol-Ung Jang

IPC分类号： G11C16/06 ,  G11C7/12 ,  G11C13/00 ,  G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  G11C7/00

CPC分类号： G11C17/126 ,  G11C7/12

摘要： Disclosed is a NOR type mask ROM device with a hierarchical bit line architecture in which metal oxide semiconductor FETs constituting memory cells are connected in parallel to one another. The mask ROM device is implemented with an address transition detection (ATD) circuit, and comprises first and second bit lines arranged in the ratio of 2:1, ground lines corresponding to the second bit lines, respectively, first switches each connected between an end of a corresponding odd-numbered bit line of the first bit lines and an end of a corresponding bit line of the second bit lines, second switches each connected between an end of a corresponding even-numbered bit line of the second bit lines and an end of a corresponding ground line of the ground lines, and a charging circuit for charging at least one adjacent non-selected bit line of the first bit lines at both sides of at least one selected bit line of the first bit lines to a predetermined voltage level, when a precharging operation is carried out to sense data through at least one selected bit line of the second bit lines.

摘要翻译： 公开了具有分层位线架构的NOR型掩模ROM器件，其中构成存储器单元的金属氧化物半导体FET彼此并联连接。 掩模ROM装置由地址转换检测（ATD）电路实现，并且包括分别以2:1的比例布置的第一和第二位线，分别对应于第二位线的接地线，第一个开关各自连接在一个端部 第一位线的对应的奇数位线和第二位线的对应位线的一端的第二开关，每个连接在第二位线的对应的偶数位线的一端和端部之间的第二开关 以及充电电路，用于将第一位线的至少一个选定位线的两侧的第一位线的至少一个相邻未选位线充电到预定电压电平 当执行预充电操作以通过第二位线的至少一个选定位线来检测数据时。

公开(公告)号：US5920519A

公开(公告)日：1999-07-06

申请号：US855256

申请日：1997-05-13

申请人： Cheol-Ung Jang

发明人： Cheol-Ung Jang

IPC分类号： G11C16/02 ,  G11C7/10 ,  G11C16/06 ,  G11C17/18 ,  G11C8/00

CPC分类号： G11C7/1021 ,  G11C7/1033

摘要： A memory having a read function for generating a plurality of data bits on a single output pin includes a control circuit, a sense amplifier circuit, and a decoder. The control circuit generates a decoder control pulse responding to the control pulse generated from an address transition detector receiving a first address. The sense amplifier circuit senses data bits from a memory array of the memory and is coupled to the output pin through a data output buffer. The decoder receives a second address and provides decoding signals to the sense amplifier circuitry in response to the control pulse generated from the control circuit. The read-out operation according to the invention is performed sufficiently and stably even when a propagation skew occurs between the first address and the second address.

摘要翻译： 具有用于在单个输出引脚上产生多个数据位的读取功能的存储器包括控制电路，读出放大器电路和解码器。 控制电路响应于从接收到第一地址的地址转换检测器产生的控制脉冲产生解码器控制脉冲。 感测放大器电路感测来自存储器的存储器阵列的数据位，并且通过数据输出缓冲器耦合到输出引脚。 解码器接收第二地址，并响应于从控制电路产生的控制脉冲向解读放大器电路提供解码信号。 即使当在第一地址和第二地址之间发生传播偏斜时，根据本发明的读出操作也被充分且稳定地执行。

公开(公告)号：US5528537A

公开(公告)日：1996-06-18

申请号：US505038

申请日：1995-07-21

申请人： Hyong-Gon Lee ,  Sang-Ki Hwang ,  Cheol-Ung Jang ,  Young-Wi Ko ,  Sung-Hee Cho

发明人： Hyong-Gon Lee ,  Sang-Ki Hwang ,  Cheol-Ung Jang ,  Young-Wi Ko ,  Sung-Hee Cho

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C17/12 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/115 ,  G11C17/123 ,  H01L27/112

摘要： A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.

摘要翻译： 具有适用于高速运行和低电源电压的单元结构的非易失性半导体存储器。 非易失性半导体存储器包括切换电路，其包括通过其相应端子连接到相应位线的块选择晶体管。 该切换电路仅在选择与开关电路对应的串时发送信号。 在构成存储晶体管的源区和漏区的第一有源区具有不同杂质浓度的第二有源区形成在连接存储器串和位线的位线接触部的衬底接触部分。 第二有源区的杂质浓度低于第一有源区的杂质浓度。

公开(公告)号：US6075734A

公开(公告)日：2000-06-13

申请号：US213616

申请日：1998-12-17

申请人： Cheol-Ung Jang

发明人： Cheol-Ung Jang

IPC分类号： G11C16/06 ,  G11C11/34 ,  G11C11/56 ,  G11C16/02 ,  G11C7/00

CPC分类号： G11C11/56 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/30 ,  G11C7/1048

摘要： Disclosed herein is an integrated circuit memory device which includes a memory cell arranged at an intersection of a word line and a bit line and a bit line precharge circuit for providing the bit line with a predetermined current during respective bit line precharge and sensing periods of time of a data reading operation in response to a bit line precharge signal. The integrated circuit memory device further includes a bit line pass transistor which has a gate and connected between the bit line precharge circuit and the bit line and which transfers the current from the bit line precharge circuit onto the bit line. Furthermore, the device includes a bias voltage supplying circuit which supplies the gate of the bit line pass transistor with a bias voltage during the data reading operation. In this embodiment, the bias voltage supplying circuit makes a voltage on the gate of the bit line pass transistor become discharged under the bias voltage during a bit line discharge period of time of the data reading operation.

摘要翻译： 本文公开了一种集成电路存储器件，其包括布置在字线和位线的交叉点处的存储器单元和位线预充电电路，用于在相应的位线预充电和感测时段期间向位线提供预定电流 响应于位线预充电信号的数据读取操作。 集成电路存储装置还包括位线传输晶体管，其具有栅极并连接在位线预充电电路和位线之间，并将电流从位线预充电电路传送到位线。 此外，该器件包括偏置电压提供电路，其在数据读取操作期间向位线通过晶体管的栅极提供偏置电压。 在本实施例中，在数据读取操作的位线放电期间，偏置电压供给电路使位线通过晶体管的栅极上的电压在偏置电压下放电。

公开(公告)号：US6044033A

公开(公告)日：2000-03-28

申请号：US221978

申请日：1998-12-29

申请人： Cheol-Ung Jang

发明人： Cheol-Ung Jang

IPC分类号： G11C17/12 ,  G11C16/00 ,  G11C16/04 ,  G11C16/26 ,  G11C8/00

CPC分类号： G11C16/26

摘要： A NOR-type read only memory with improved read-out performance includes a memory cell array having a plurality of memory cell blocks, each memory block including a plurality of bit lines, a column decoder for generating a plurality of decoding signals in response to a plurality of address signals, a first bias/ground selection control circuit for generating a plurality of first bias/ground selection signals determining bias conditions for a first group of the plurality of bit lines, a first bias/ground selection circuit for establishing bias conditions of the first group of the plurality of bit lines in response to the first bias/ground selection signals generated from the first bias/ground selection control circuit, a second bias/ground selection control circuit for generating a plurality of second bias/ground selection signals determining bias conditions of a second group of the plurality of bit lines, and a second bias/ground selection circuit for establishing bias conditions of the second group of the plurality of bit lines in response to the second bias/ground selection signals generated from the second bias/ground selection control circuit.

摘要翻译： 具有改进的读出性能的NOR型只读存储器包括具有多个存储单元块的存储单元阵列，每个存储块包括多个位线，列解码器，用于响应于 多个地址信号;第一偏置/接地选择控制电路，用于产生确定多个位线的第一组的偏置条件的多个第一偏置/接地选择信号;第一偏置/地选择电路，用于建立 响应于从第一偏置/接地选择控制电路产生的第一偏置/接地选择信号，多个位线中的第一组;第二偏置/接地选择控制电路，用于产生多个第二偏置/地选择信号， 所述多个位线的第二组的偏置条件，以及用于建立所述多个位线的偏置条件的第二偏置/地选择电路 响应于从第二偏置/接地选择控制电路产生的第二偏置/接地选择信号，多个位线的第二组。

公开(公告)号：US5635747A

公开(公告)日：1997-06-03

申请号：US481098

申请日：1995-06-07

申请人： Hyong-Gon Lee ,  Sang-Ki Hwang ,  Cheol-Ung Jang ,  Young-Wi Ko ,  Sung-Hee Cho

发明人： Hyong-Gon Lee ,  Sang-Ki Hwang ,  Cheol-Ung Jang ,  Young-Wi Ko ,  Sung-Hee Cho

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C17/12 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/115 ,  G11C17/123 ,  H01L27/112

摘要： A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.

摘要翻译： 具有适用于高速运行和低电源电压的单元结构的非易失性半导体存储器。 非易失性半导体存储器包括切换电路，其包括通过其相应端子连接到相应位线的块选择晶体管。 该切换电路仅在选择与开关电路对应的串时发送信号。 在构成存储晶体管的源区和漏区的第一有源区具有不同杂质浓度的第二有源区形成在连接存储器串和位线的位线接触部的衬底接触部分。 第二有源区的杂质浓度低于第一有源区的杂质浓度。

公开(公告)号：US6069831A

公开(公告)日：2000-05-30

申请号：US103964

申请日：1998-06-24

申请人： Cheol-Ung Jang ,  Byeng-Soon Choi

发明人： Cheol-Ung Jang ,  Byeng-Soon Choi

IPC分类号： G11C17/18 ,  G11C7/06 ,  G11C7/14 ,  G11C7/18 ,  G11C11/416 ,  G11C16/04 ,  G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  G11C7/02

CPC分类号： G11C7/14 ,  G11C17/12 ,  G11C7/062 ,  G11C7/18

摘要： A semiconductor read-only memory includes a main memory cell array having a plurality of first and second bit lines arranged in a hierarchical configuration. A dummy cell array generates a reference potential during a read-out operation. A decoder circuit generates a first, second, third and fourth selection signals from address signals, and a sense amplifier circuit detects data stored in a memory cell of the main memory cell array. A switching circuit connects the dummy cell to the sense amplifier circuit through the second bit line. The read-only memory according to the invention has an advantage that it is possible to accomplish an efficient read-out operation without additional dummy bit lines in an area of the memory cell array.

摘要翻译： 半导体只读存储器包括具有以分层结构布置的多个第一和第二位线的主存储单元阵列。 虚拟单元阵列在读出操作期间产生参考电位。 解码器电路从地址信号产生第一，第二，第三和第四选择信号，并且读出放大器电路检测存储在主存储单元阵列的存储单元中的数据。 开关电路通过第二位线将虚拟单元连接到读出放大器电路。 根据本发明的只读存储器具有这样的优点：可以在存储单元阵列的区域中没有附加的虚位线来实现高效的读出操作。

公开(公告)号：US5672989A

公开(公告)日：1997-09-30

申请号：US590602

申请日：1996-01-24

申请人： Cheol-Ung Jang ,  Hyong-Gon Lee ,  Sung-Hee Cho

发明人： Cheol-Ung Jang ,  Hyong-Gon Lee ,  Sung-Hee Cho

IPC分类号： G11C11/41 ,  G06F11/00 ,  G11C5/14 ,  G11C8/00 ,  G11C8/18 ,  G11C11/408 ,  G11C14/00 ,  G11C16/02 ,  G11C16/06 ,  G11C17/00 ,  G11C17/18 ,  H01L27/00 ,  H03L7/00

CPC分类号： G11C5/143 ,  G11C8/18

摘要： A semiconductor integrated circuit having an address transition detector includes a power detecting circuit connected to a source terminal for detecting a voltage level of the source terminal, a pulse generating circuit for receiving an address signal and generating a pulse when the address signal is changed, and a summator for combining outputs of the power detecting circuit and the pulse generating circuit and generating a given pulse when the outputs vary.

摘要翻译： 具有地址转换检测器的半导体集成电路包括连接到用于检测源极端子的电压电平的源极端子的功率检测电路，用于接收地址信号并在地址信号改变时产生脉冲的脉冲发生电路，以及 用于组合功率检测电路和脉冲发生电路的输出并在输出变化时产生给定脉冲的加法器。