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1.发明授权Process for producing an integrated electronic circuit comprising superposed components and integrated electronic circuit thus obtained 有权一种集成电子电路的制造方法，包括由此获得的重叠部件和集成电子电路公开(公告)号：US07202137B2
公开(公告)日：2007-04-10
申请号：US10850040
申请日：2004-05-20
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L21/76264 , H01L29/66772 , H01L29/78648
摘要： A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.
摘要翻译： 一种集成电子电路的制造方法。 该过程开始于重叠在基板顶部上的第一电子部件和第二电子部件的制造。 在第二电子部件的位置处，在基板上形成一定量的临时材料。 然后在临时材料的体积上方相对于基板制造第一电子部件，然后使用至少一个轴来制造第二电子部件，用于接近临时材料。 第一电子部件可以是有源部件，第二电子部件可以是无源部件。
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2.发明申请Process for producing an integrated electronic circuit comprising superposed components and integrated electronic circuit thus obtained 有权一种集成电子电路的制造方法，包括由此获得的重叠部件和集成电子电路公开(公告)号：US20050037593A1
公开(公告)日：2005-02-17
申请号：US10850040
申请日：2004-05-20
IPC分类号： H01L21/02 , H01L21/336 , H01L21/762 , H01L29/786 , H01L21/76
CPC分类号： H01L28/40 , H01L21/76264 , H01L29/66772 , H01L29/78648
摘要： A process for producing an integrated electronic circuit comprises the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.
摘要翻译： 一种用于制造集成电子电路的方法包括制造叠置在基板顶部上的第一电子部件和第二电子部件。 在第二电子部件的位置处，在基板上形成一定量的临时材料。 然后在临时材料的体积上方相对于基板制造第一电子部件，然后使用至少一个轴来制造第二电子部件，用于接近临时材料。 第一电子部件可以是有源部件，第二电子部件可以是无源部件。
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公开(公告)号：US07378692B2
公开(公告)日：2008-05-27
申请号：US11412270
申请日：2006-04-27
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L28/40 , H01L21/76264 , H01L29/66772 , H01L29/78648
摘要： An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed within a volume of substantially single-crystal semiconductor material disposed on top of the passive component.
摘要翻译： 一种具有至少一个无源电子部件和至少一个有源电子部件的集成电子电路。 被动电子部件形成在设置在基板上的绝缘材料内。 活性组分形成在设置在无源组件顶部上的基本单晶半导体材料的体积内。
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公开(公告)号：US20060189057A1
公开(公告)日：2006-08-24
申请号：US11412270
申请日：2006-04-27
IPC分类号： H01L21/8234
CPC分类号： H01L28/40 , H01L21/76264 , H01L29/66772 , H01L29/78648
摘要： An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed within a volume of substantially single-crystal semiconductor material disposed on top of the passive component.
摘要翻译： 一种具有至少一个无源电子部件和至少一个有源电子部件的集成电子电路。 被动电子部件形成在设置在基板上的绝缘材料内。 活性组分形成在设置在无源组件顶部上的基本单晶半导体材料的体积内。
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5.发明授权Process for producing an integrated electronic circuit that includes a capacitor 有权一种包括电容器的集成电子电路的制造方法公开(公告)号：US07033887B2
公开(公告)日：2006-04-25
申请号：US10850042
申请日：2004-05-20
IPC分类号： H01L21/8242
CPC分类号： H01L28/60
摘要： A process for producing an integrated electronic circuit that includes a capacitor comprises the formation of a stack on top of a substrate (100, 101). The stack comprises a first volume of a temporary material, a second volume (2) of at least one insulating dielectric and a third volume (3) of a first electrically conducting material. After a coating material (4) has been deposited on the stack, the temporary material is removed via access shafts (C1, C2) that are formed between a surface (S) of the circuit and the first volume. The temporary material is then replaced with a second, electrically conducting material.
摘要翻译： 一种用于制造包括电容器的集成电子电路的方法包括在衬底（100,101）的顶部上形成叠层。 堆叠包括第一体积的临时材料，至少一个绝缘电介质的第二体积（2）和第一导电材料的第三体积（3）。 在涂层材料（4）已经沉积在堆叠上之后，临时材料通过形成在电路的表面（S）和第一体积之间的存取轴（C 1，C 2）去除。 然后用第二导电材料代替临时材料。
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6.发明申请Process for producing an integrated electronic circuit that includes a capacitor 有权一种包括电容器的集成电子电路的制造方法公开(公告)号：US20050032303A1
公开(公告)日：2005-02-10
申请号：US10850042
申请日：2004-05-20
IPC分类号： H01L21/02 , H01L29/92 , H01L21/8234
CPC分类号： H01L28/60
摘要： A process for producing an integrated electronic circuit that includes a capacitor comprises the formation of a stack on top of a substrate (100, 101). The stack comprises a first volume of a temporary material, a second volume (2) of at least one insulating dielectric and a third volume (3) of a first electrically conducting material. After a coating material (4) has been deposited on the stack, the temporary material is removed via access shafts (C1, C2) that are formed between a surface (S) of the circuit and the first volume. The temporary material is then replaced with a second, electrically conducting material.
摘要翻译： 一种用于制造包括电容器的集成电子电路的方法包括在衬底（100,101）的顶部上形成叠层。 堆叠包括第一体积的临时材料，至少一个绝缘电介质的第二体积（2）和第一导电材料的第三体积（3）。 在涂层材料（4）已经沉积在堆叠上之后，临时材料通过形成在电路的表面（S）和第一体积之间的接近轴（C1，C2）去除。 然后用第二导电材料代替临时材料。
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7.发明申请公开(公告)号：US20090040684A1
公开(公告)日：2009-02-12
申请号：US12134490
申请日：2008-06-06
CPC分类号： H01L28/87 , H01L28/91 , Y10T29/417
摘要： The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.
摘要翻译： 用于形成具有至少一个二维或三维电容器的微电子器件的方法包括在衬底上产生多个部件和多个叠加的金属互连电平。 在金属互连层上形成绝缘层，在其中形成有一个或多个由该绝缘层形成的绝缘块的下一个金属互连层的水平金属区。 该区域被设计成形成电容器的下部结构部分。
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公开(公告)号：US20060234464A1
公开(公告)日：2006-10-19
申请号：US11405680
申请日：2006-04-17
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L28/91 , H01L21/76838 , H01L21/76895 , H01L23/5223 , H01L28/40 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form the trenches. A layer of conductive material forming the lower electrode of the capacitor is then deposited at least on the sidewalls of the trenches and in contact with the metal layer. A dielectric layer is then deposited within the trenches. A layer of conductive material forming the upper electrode of the capacitor is then deposited within the trenches.
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9.发明申请Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit 有权通过在集成电路的互连电介质层中使用金属沉积物来制造电容器的方法公开(公告)号：US20060160319A1
公开(公告)日：2006-07-20
申请号：US11302971
申请日：2005-12-14
IPC分类号： H01L21/20
CPC分类号： H01L21/32139 , H01L21/84 , H01L23/5223 , H01L27/13 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (21); Deposit of a first insulator layer (31) on the first metallic layer (21); Deposit of a second metallic layer (41) on the first insulator layer (31); Formation of an upper electrode (4) in the second layer metallic (41); Deposit of a second insulator layer (13) covering the upper electrode (4); Etching of the second insulator layer to form a spacer (14) on this first insulator layer surrounding the upper electrode (4); then Formation of a lower electrode (2) and a dielectric (3) by removal of parts from the first metallic layer and insulator not covered by the upper electrode (4) or the spacer (14); and Formation of an interconnection line (5). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.
摘要翻译： 互连层中的电容器的制造方法包括以下阶段：第一金属层（21）的沉积; 在第一金属层（21）上沉积第一绝缘体层（31）; 在第一绝缘体层（31）上沉积第二金属层（41）; 在第二层金属（41）中形成上电极（4）; 沉积覆盖上电极（4）的第二绝缘体层（13）。 蚀刻第二绝缘体层以在围绕上电极（4）的该第一绝缘体层上形成间隔物（14）; 然后通过从第一金属层和未被上电极（4）或间隔物（14）覆盖的绝缘体去除零件来形成下电极（2）和电介质（3）; 和互连线（5）的形成。 该过程允许以更低的成本和自动对准以简化的方式制造具有增加的性能的电容器。
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公开(公告)号：US06271574B1
公开(公告)日：2001-08-07
申请号：US09310264
申请日：1999-05-12
申请人： Philippe Delpech , Nathalie Revil
发明人： Philippe Delpech , Nathalie Revil
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit fuse includes a substantially bar-shaped central region and zones having electrical contacts. The central region includes a thinned zone forming a weak point facilitating fusing of the fuse by increasing the local current density as compared to standard fusing conditions. The thinned zone is preferably obtained by proximity optical effect between the fuse and adjacent dummy elements.
摘要翻译： 集成电路熔断器包括大致条形中心区域和具有电触点的区域。 中心区域包括形成弱点的薄区，与标准熔化条件相比，通过增加局部电流密度便于保险丝的熔合。 优选通过熔丝和相邻虚设元件之间的接近光学效应来获得变薄区。
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