公开(公告)号：US08440567B2

公开(公告)日：2013-05-14

申请号：US13033268

申请日：2011-02-23

申请人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

发明人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

IPC分类号： H01L21/302

CPC分类号： H01L21/768 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/12 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2924/00

摘要： Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

摘要翻译： 一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。 随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。 跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。 在一些实施例中，等离子体增强的原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

公开(公告)号：US07915168B2

公开(公告)日：2011-03-29

申请号：US12721398

申请日：2010-03-10

申请人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

发明人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

IPC分类号： H01L21/302

CPC分类号： H01L21/768 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/12 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2924/00

摘要： Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

摘要翻译： 一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。 随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。 跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。 在一些实施例中，等离子体增强的原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

公开(公告)号：US20100167521A1

公开(公告)日：2010-07-01

申请号：US12721398

申请日：2010-03-10

申请人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

发明人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

IPC分类号： H01L21/768

CPC分类号： H01L21/768 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/12 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2924/00

摘要： Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

摘要翻译： 一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。 随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。 跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。 在一些实施例中，等离子体增强的原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

公开(公告)号：US20090258485A1

公开(公告)日：2009-10-15

申请号：US12101332

申请日：2008-04-11

申请人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

发明人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

IPC分类号： H01L21/44

CPC分类号： H01L21/768 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/12 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2924/00

摘要： Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

摘要翻译： 一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。 随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。 跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。 在一些实施例中，等离子体增强的原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

公开(公告)号：US20110143538A1

公开(公告)日：2011-06-16

申请号：US13033268

申请日：2011-02-23

申请人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

发明人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

IPC分类号： H01L21/768

CPC分类号： H01L21/768 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/12 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2924/00

摘要： Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

摘要翻译： 一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。 随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。 跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。 在一些实施例中，等离子体增强的原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

公开(公告)号：US07704884B2

公开(公告)日：2010-04-27

申请号：US12101332

申请日：2008-04-11

申请人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

发明人： Junting Liu ,  Er-Xuan Ping ,  Seiichi Takedai

IPC分类号： H01L21/302

CPC分类号： H01L21/768 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/12 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2924/00

摘要： Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

摘要翻译： 一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。 随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。 跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。 在一些实施例中，等离子体增强的原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

公开(公告)号：US5559350A

公开(公告)日：1996-09-24

申请号：US350156

申请日：1994-11-29

申请人： Thoru Ozaki ,  Kazumasa Sunouchi ,  Seiichi Takedai ,  Yoshiyuki Shioyama

发明人： Thoru Ozaki ,  Kazumasa Sunouchi ,  Seiichi Takedai ,  Yoshiyuki Shioyama

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A dynamic RAM array comprises a substrate, a plurality of semiconductor island regions and a trench region formed on the substrate, each island region being surrounded by the trench region, and the trench region having wider trench portions and narrower trench portions, an insulating layer formed on the trench region, capacitors refilled in the wider trench portions, each capacitor having a plate electrode, a capacitor insulating layer and a storage node electrode, refilled layers formed in the narrower trench portion, for forming field isolation regions, MOS transistors formed on the island region, each MOS transistor having a source, a drain and a gate as word line, one of the source and drain being coupled with the storage node electrode, and bit lines perpendicular to the word line, being coupled with the other of the source and drain.

摘要翻译： 动态RAM阵列包括基板，多个半导体岛区域和形成在基板上的沟槽区域，每个岛区域被沟槽区域包围，并且沟槽区域具有较宽的沟槽部分和较窄的沟槽部分，形成绝缘层 在沟槽区域中，在较宽的沟槽部分中重新填充电容器，每个电容器具有平板电极，电容器绝缘层和存储节点电极，形成在较窄沟槽部分中的再填充层，用于形成场隔离区域，形成在 岛区域，每个MOS晶体管具有源极，漏极和栅极作为字线，源极和漏极中的一个与存储节点电极耦合，以及垂直于字线的位线，与源极中的另一个耦合 和排水。