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    Data driven processor with data pairing apparatus combining a hash memory with counter directional data loops
    1.
    发明授权
    Data driven processor with data pairing apparatus combining a hash memory with counter directional data loops 失效
    数据驱动处理器与数据配对设备组合哈希存储器与反向数据循环

    公开(公告)号：US5072377A

    公开(公告)日：1991-12-10

    申请号：US121516

    申请日：1987-11-17

    申请人： Fumiyasu Asai ,  Shinji Komori

    发明人： Fumiyasu Asai ,  Shinji Komori

    IPC分类号： G06F15/82 ,  G06F9/44 ,  G06F12/00

    CPC分类号： G06F9/4436

    摘要： A data driven processing system includes a mechanism for generating a data pair from a sequential input data stream by matching identifier fields. The pairing mechanism comprises a hash memory in which input data words to be paired are stored by using hashed addresses. If a hash collision occurs, the data word which caused the hash collision is transmitted to a counter-directional data loop which is used to generate a data pair. If an input data word is not paired after one pass through the data loop it is returned to the hash memory for another pairing operation. Use of both the hash memory and the counter-directional data loop reduces the required hash memory size and increases processing efficiency.

    摘要翻译： 数据驱动处理系统包括用于通过匹配标识符字段从顺序输入数据流生成数据对的机制。 配对机制包括散列存储器，其中通过使用散列地址来存储要配对的输入数据字。 如果发生哈希冲突，则导致哈希冲突的数据字被发送到用于生成数据对的逆向数据循环。 如果输入数据字在一次通过数据循环后未配对，则返回到哈希存储器进行另一次配对操作。 使用散列存储器和逆向数据环路都可以减少所需的散列存储器大小并提高处理效率。

    Data-driven processor having an internal tag-generating system for generating a distinct tagged information and assembling with un-tagged information of an input/output data packet
    2.
    发明授权
    Data-driven processor having an internal tag-generating system for generating a distinct tagged information and assembling with un-tagged information of an input/output data packet 失效
    数据驱动处理器具有内部标签生成系统，用于生成不同的标记信息并且与输入/输出数据包的未标记信息进行组合

    公开(公告)号：US5117489A

    公开(公告)日：1992-05-26

    申请号：US471684

    申请日：1990-01-26

    申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

    发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

    IPC分类号： G06F9/44

    CPC分类号： G06F9/4436

    摘要： A data-driven processor which has a packet assembling unit to add a tag information to the sequentially inputted data when the input data has no tag information, such as destination address or the like, thereby enabling the data to be inputted without using an external circuit, such as a host processor, and improving the data input rate and which also has a packet outputting and rearranging unit for rearranging an output packet stream in a predetermined order to thereby output the data information only, so that it is possible that the data is outputted without any external circuit, such as a host processor, the output rate is improved and the data output is executed in a predetermined order.

    摘要翻译： 数据驱动处理器具有分组组合单元，用于当输入数据不具有诸如目的地址等的标签信息时，将标签信息添加到顺序输入的数据，从而使得能够在不使用外部电路的情况下输入数据 ，诸如主处理器，并且提高数据输入速率，并且还具有分组输出和重排单元，用于以预定顺序重新排列输出分组流，从而仅输出数据信息，使得数据可能是 在没有任何外部电路的情况下输出，例如主机处理器，输出速率得到改善，并且以预定顺序执行数据输出。

    Reduced power pipelined static data transfer apparatus
    4.
    发明授权
    Reduced power pipelined static data transfer apparatus 失效
    降低功率流水线静态数据传输设备

    公开(公告)号：US4980851A

    公开(公告)日：1990-12-25

    申请号：US284963

    申请日：1988-12-15

    申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Tetsuo Yamasaki ,  Kenji Shima

    发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Tetsuo Yamasaki ,  Kenji Shima

    IPC分类号： G06F13/38 ,  G06F5/08 ,  G06F13/42 ,  G11C7/00

    CPC分类号： G06F13/4213 ,  Y02B60/1228 ,  Y02B60/1235

    摘要： A pipelined processor is provided with a plurality of control stages controlling a datapath made up of a plurality of parallel static-type data latches. The latches each include a feedback circuit, typically a field-effect transistor, which is enabled by a data latch control signal from a particular control stage. Enabling the feedback stage consumes power. A data stagnation detection circuit detects a data stagnation in the datapath, by use of handshake control signals exchanged between the control stages. The data stagnation detection circuit inhibits enablement of the feedback circuit when no data stagnation is detected, reducing power used in the latch.

    摘要翻译： 流水线处理器设置有多个控制级，控制由多个并行静态数据锁存器组成的数据路径。 锁存器各自包括反馈电路，通常是场效应晶体管，其通过来自特定控制级的数据锁存器控制信号使能。 启用反馈级消耗电力。 数据停滞检测电路通过使用在控制级之间交换的握手控制信号来检测数据通路中的数据停滞。 当没有检测到数据停滞时，数据停滞检测电路禁止反馈电路的使能，减少锁存器中使用的功率。

    Data-driven processor having an output unit for providing only operand data in a predetermined order
    6.
    发明授权
    Data-driven processor having an output unit for providing only operand data in a predetermined order 失效
    数据驱动处理器具有用于仅以预定顺序提供操作数数据的输出单元

    公开(公告)号：US5392442A

    公开(公告)日：1995-02-21

    申请号：US837128

    申请日：1992-02-19

    申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

    发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

    IPC分类号： E04B1/41 ,  F16B13/08 ,  F16B13/14 ,  G06F9/06

    CPC分类号： F16B13/0808 ,  Y10S411/908

    摘要： A data-driven processor which has a packet assembling unit to add a tag information to the sequentially inputted data when the input data has no tag information, such as destination address or the like, thereby enabling the data to be inputted without using an external circuit, such as a host processor, and improving the data input rate and which also has a packet outputting and rearranging unit for rearranging an output packet stream in a predetermined order to thereby output the data information only, so that it is possible that the data is outputted without any external circuit, such as a host processor, the output rate is improved, and the data output is executed in a predetermined order.

    摘要翻译： 数据驱动处理器具有分组组合单元，用于当输入数据不具有诸如目的地址等的标签信息时，将标签信息添加到顺序输入的数据，从而使得能够在不使用外部电路的情况下输入数据 ，诸如主处理器，并且提高数据输入速率，并且还具有分组输出和重排单元，用于以预定顺序重新排列输出分组流，从而仅输出数据信息，使得数据可能是 在没有任何外部电路的情况下输出，诸如主处理器，输出速率得到改善，并且以预定顺序执行数据输出。

    Hand-shake type data transfer control circuit
    7.
    发明授权
    Hand-shake type data transfer control circuit 失效
    手抖式数据传输控制电路

    公开(公告)号：US4882704A

    公开(公告)日：1989-11-21

    申请号：US157194

    申请日：1988-02-17

    申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai

    发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai

    IPC分类号： G06F13/42 ,  H04J3/04

    CPC分类号： G06F7/00 ,  G06F13/4213 ,  H04J3/047 ,  G06F2207/3864

    摘要： A hand-shake type control circuit for controlling a data transfer circuit according to the status of a data transfer request signal. The data transfer request signal is initially received at a NAND gate and is also directly coupled to the reset input of are set flip-flop. The output of the NAND gate is used as a first control signal to set the flip-flop and to cause another circuit to activate data transfer. The flip-flop output is a second control signal which is reset only when the transfer request signal changes from an active to an inactive status. The second control signal is coupled to an input of the NAND gate and inactivates the first control signal. Thus, data transfer cannot recur until after the data transfer request signal changes to an inactive status so that parasitic oscillations are eliminated. The flip-flop consists of two, two input NAND gates that are located out of the path of data transfer and that are easier to fabricate than the prior art D flip-flop.

    摘要翻译： 一种用于根据数据传送请求信号的状态控制数据传送电路的握手型控制电路。 数据传送请求信号最初在NAND门处被接收并且也直接耦合到被设置的触发器的复位输入。 NAND门的输出用作第一控制信号以设置触发器并使另一电路激活数据传输。 触发器输出是仅在传送请求信号从活动状态变为非活动状态时才复位的第二控制信号。 第二控制信号耦合到NAND门的输入并使第一控制信号无效。 因此，在数据传输请求信号变为无效状态之后，数据传送不能重复，以便消除寄生振荡。 触发器由两个，两个输入NAND门组成，它们位于数据传输路径之外，并且比现有技术的D触发器更容易制造。