中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.014 seconds)

    Semiconductor device with its test time reduced and a test method therefor
    1.
    发明申请
    Semiconductor device with its test time reduced and a test method therefor 有权
    其测试时间缩短的半导体器件及其测试方法

    公开(公告)号：US20080071486A1

    公开(公告)日：2008-03-20

    申请号：US11797698

    申请日：2007-05-07

    Applicant: Hideo Ikejiri ,  Shinsuke Onishi

    Inventor： Hideo Ikejiri ,  Shinsuke Onishi

    IPC: G06F19/00 ,  G01R19/00 ,  G01R21/06

    CPC classification number: G01R31/318357 ,  G01R31/318385

    Abstract: In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The voltage regulator is halted by a power-down signal. Testing is then carried out as the test supply voltage is applied to the second logics. When plural test items are executed successively, a test reset signal is applied to a test reset terminal for each item. As the initialized state of the register is canceled, the first and second logics are initialized.

    Abstract translation: 在半导体器件中，当电压调节器停止工作并将测试电源电压提供给第二逻辑时，器件由复位信号初始化。 然后通过第一逻辑通过输入信号复位器件中包含的寄存器。 电压调节器由掉电信号停止。 随着测试电源电压被施加到第二逻辑，然后进行测试。 当连续执行多个测试项目时，将测试复位信号应用于每个项目的测试复位终端。 由于寄存器的初始化状态被取消，初始化第一和第二逻辑。

    WORKPIECE PUNCH-MOLDING METHOD AND WORKPIECE PUNCH-MOLDING DEVICE
    3.
    发明申请
    WORKPIECE PUNCH-MOLDING METHOD AND WORKPIECE PUNCH-MOLDING DEVICE 审中-公开
    工作冲压成型方法和工件冲压成型装置

    公开(公告)号：US20130227999A1

    公开(公告)日：2013-09-05

    申请号：US13517073

    申请日：2011-11-24

    Applicant: Shinsuke Onishi ,  Masaaki Fujita ,  Shintaro Nakamura ,  Naoya Nemoto ,  Naruhiko Okubo

    Inventor： Shinsuke Onishi ,  Masaaki Fujita ,  Shintaro Nakamura ,  Naoya Nemoto ,  Naruhiko Okubo

    IPC: B21D28/02 ,  B21D28/24

    CPC classification number: B21D28/02 ,  B21D28/16 ,  B21D28/24

    Abstract: Provided is a workpiece punch-molding method and a workpiece punch-molding device capable of maintaining the thickness of a workpiece at a constant precision. Prior to the punch of a workpiece by a mold punch and a counter punch, the data denoting a relationship between a punch speed of the mold punch and a delay time of the depressurization of the counter punch is obtained. The counter punch is subjected to the depressurization at an early timing based on the obtained data.

    Abstract translation: 本发明提供能够以一定的精度保持工件的厚度的工件冲压成型方法和工件冲压成型装置。 在通过模具冲头和反冲头冲压工件之前，获得表示冲模冲头速度与计数冲头的减压延迟时间之间的关系的数据。 基于所获得的数据，按照早期定时对计数器冲头进行减压。

    Semiconductor device with its test time reduced and a test method therefor
    4.
    发明授权
    Semiconductor device with its test time reduced and a test method therefor 有权
    其测试时间缩短的半导体器件及其测试方法

    公开(公告)号：US07724024B2

    公开(公告)日：2010-05-25

    申请号：US12479083

    申请日：2009-06-26

    Applicant: Hideo Ikejiri ,  Shinsuke Onishi

    Inventor： Hideo Ikejiri ,  Shinsuke Onishi

    IPC: H03K19/00

    CPC classification number: G01R31/318357 ,  G01R31/318385

    Abstract: In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The voltage regulator is halted by a power-down signal. Testing is then carried out as the test supply voltage is applied to the second logics. When plural test items are executed successively, a test reset signal is applied to a test reset terminal for each item. As the initialized state of the register is canceled, the first and second logics are initialized.

    Abstract translation: 在半导体器件中，当电压调节器停止工作并将测试电源电压提供给第二逻辑时，器件由复位信号初始化。 然后通过第一逻辑通过输入信号复位器件中包含的寄存器。 电压调节器由掉电信号停止。 随着测试电源电压被施加到第二逻辑，然后进行测试。 当连续执行多个测试项目时，将测试复位信号应用于每个项目的测试复位终端。 由于寄存器的初始化状态被取消，初始化第一和第二逻辑。

    Amplification circuit and oscillation circuit including inverter circuits having a same threshold voltage
    5.
    发明授权
    Amplification circuit and oscillation circuit including inverter circuits having a same threshold voltage 有权
    包括具有相同阈值电压的反相电路的放大电路和振荡电路

    公开(公告)号：US07106139B2

    公开(公告)日：2006-09-12

    申请号：US10173925

    申请日：2002-06-19

    Applicant: Masashi Morimoto ,  Shinsuke Onishi

    Inventor： Masashi Morimoto ,  Shinsuke Onishi

    IPC: H03L7/085

    CPC classification number: H03F3/345 ,  H03F3/72 ,  H03K3/3545

    Abstract: A first inverter includes a plurality of first gate elements having first gate electrodes which extend in a first direction. A second inverter includes a plurality of second gate elements having second gate electrodes which extend in the first direction. A gate length of the first gate electrodes is the same as a gate length of the second gate electrodes, and a gate width of the first gate electrodes which is defined by a first active region, is the same as a gate width of the second gate electrodes which is defined by a second active region.

    Abstract translation: 第一反相器包括具有沿第一方向延伸的第一栅电极的多个第一栅极元件。 第二反相器包括具有在第一方向上延伸的第二栅电极的多个第二栅极元件。 第一栅电极的栅极长度与第二栅电极的栅极长度相同，由第一有源区限定的第一栅电极的栅极宽度与第二栅极的栅极宽度相同 由第二活性区域限定的电极。

    SEMICONDUCTOR DEVICE WITH ITS TEST TIME REDUCED AND A TEST METHOD THEREFOR
    7.
    发明申请
    SEMICONDUCTOR DEVICE WITH ITS TEST TIME REDUCED AND A TEST METHOD THEREFOR 有权
    具有减少测试时间的半导体器件及其测试方法

    公开(公告)号：US20090251170A1

    公开(公告)日：2009-10-08

    申请号：US12479083

    申请日：2009-06-26

    Applicant: Hideo IKEJIRI ,  Shinsuke ONISHI

    Inventor： Hideo IKEJIRI ,  Shinsuke ONISHI

    IPC: H03K19/00 ,  H03K19/0175

    CPC classification number: G01R31/318357 ,  G01R31/318385

    Abstract: In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The voltage regulator is halted by a power-down signal. Testing is then carried out as the test supply voltage is applied to the second logics. When plural test items are executed successively, a test reset signal is applied to a test reset terminal for each item. As the initialized state of the register is canceled, the first and second logics are initialized.

    Abstract translation: 在半导体器件中，当电压调节器停止工作并将测试电源电压提供给第二逻辑时，器件由复位信号初始化。 然后通过第一逻辑通过输入信号复位器件中包含的寄存器。 电压调节器由掉电信号停止。 随着测试电源电压被施加到第二逻辑，然后进行测试。 当连续执行多个测试项目时，将测试复位信号应用于每个项目的测试复位终端。 由于寄存器的初始化状态被取消，初始化第一和第二逻辑。

    Semiconductor device with its test time reduced and a test method therefor
    9.
    发明授权
    Semiconductor device with its test time reduced and a test method therefor 有权
    其测试时间缩短的半导体器件及其测试方法

    公开(公告)号：US07564265B2

    公开(公告)日：2009-07-21

    申请号：US11797698

    申请日：2007-05-07

    Applicant: Hideo Ikejiri ,  Shinsuke Onishi

    Inventor： Hideo Ikejiri ,  Shinsuke Onishi

    IPC: H03K19/00

    CPC classification number: G01R31/318357 ,  G01R31/318385

    Abstract: In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The voltage regulator is halted by a power-down signal. Testing is then carried out as the test supply voltage is applied to the second logics. When plural test items are executed successively, a test reset signal is applied to a test reset terminal for each item. As the initialized state of the register is canceled, the first and second logics are initialized.

    Abstract translation: 在半导体器件中，当电压调节器停止工作并将测试电源电压提供给第二逻辑时，器件由复位信号初始化。 然后通过第一逻辑通过输入信号复位器件中包含的寄存器。 电压调节器由掉电信号停止。 随着测试电源电压被施加到第二逻辑，然后进行测试。 当连续执行多个测试项目时，将测试复位信号应用于每个项目的测试复位终端。 由于寄存器的初始化状态被取消，初始化第一和第二逻辑。

    Input circuit for mode setting
    10.
    发明授权
    Input circuit for mode setting 失效
    模式设定输入电路

    公开(公告)号：US07557604B2

    公开(公告)日：2009-07-07

    申请号：US11119899

    申请日：2005-05-03

    Applicant: Shinsuke Onishi ,  Tsuguto Maruko

    Inventor： Shinsuke Onishi ,  Tsuguto Maruko

    IPC: H03K19/177

    CPC classification number: H03K19/1732

    Abstract: An input circuit for mode setting, comprising: a chip selection terminal that is operable both in first and second operation modes; a mode setting terminal that is used to select an operation mode from between the first and second operation modes; a logic holding circuit that holds a logic status at the mode setting terminal; and a control circuit that controls the logic holding circuit in accordance with a signal supplied to the chip selection terminal. Operation modes to be selected may be serial interface mode and parallel interface mode.

    Abstract translation: 一种用于模式设置的输入电路，包括：芯片选择端子，其可在第一和第二操作模式中操作; 用于从第一和第二操作模式之间选择操作模式的模式设置终端; 逻辑保持电路，在模式设定端子保持逻辑状态; 以及根据提供给芯片选择端的信号来控制逻辑保持电路的控制电路。 要选择的操作模式可以是串行接口模式和并行接口模式。

Patent Agency Ranking