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    Anti-reflective coatings for use at 248 nm and 193 nm
    1.
    发明授权
    Anti-reflective coatings for use at 248 nm and 193 nm 有权
    抗反射涂层用于248 nm和193 nm

    公开(公告)号：US06686272B1

    公开(公告)日：2004-02-03

    申请号：US10020084

    申请日：2001-12-13

    申请人： Sang-Yun Lee ,  Masaichi Eda ,  Hongqiang Lu ,  Wei-Jen Hsia ,  Wilbur G. Catabay ,  Hiroaki Takikawa ,  Yongbae Kim

    发明人： Sang-Yun Lee ,  Masaichi Eda ,  Hongqiang Lu ,  Wei-Jen Hsia ,  Wilbur G. Catabay ,  Hiroaki Takikawa ,  Yongbae Kim

    IPC分类号： H01L214763

    CPC分类号： H01L21/02126 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/0276 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/931 ,  Y10S438/952

    摘要： The present invention is directed to a silicon carbide anti-reflective coating (ARC) and a silicon oxycarbide ARC. Another embodiment is directed to a silicon oxycarbide ARC that is treated with oxygen plasma. The invention includes method embodiments for forming silicon carbide layers and silicon oxycarbide layers as ARC's on a semiconductor substrate surface. Particularly, the methods include introducing methyl silane materials into a process chamber where they are ignited as plasma and deposited onto the substrate surface as silicon carbide. Another method includes introducing methyl silane precursor materials with an inert carrier gas into the process chamber with oxygen. These materials are ignited into a plasma, and silicon oxycarbide material is deposited onto the substrate. By regulating the oxygen flow rate, the optical properties of the silicon oxycarbide layer can be adjusted. In another embodiment, the silicon oxycarbide layer can be treated with oxygen plasma.

    摘要翻译： 本发明涉及碳化硅抗反射涂层（ARC）和碳氧化硅ARC。 另一个实施方案涉及用氧等离子体处理的碳氧化硅ARC。 本发明包括在半导体衬底表面上形成碳化硅层和碳氧化硅层作为ARC的方法实施例。 特别地，所述方法包括将甲基硅烷材料引入处理室中，其中它们被等离子体点燃并作为碳化硅沉积在基板表面上。 另一种方法包括将具有惰性载气的甲基硅烷前体材料用氧气引入到处理室中。 将这些材料点燃到等离子体中，并将​​碳氧化硅材料沉积到基底上。 通过调节氧气流速，可以调节碳硅氧烷层的光学性能。 在另一个实施方案中，可以用氧等离子体处理碳氧化硅层。

    Reduced dry etching lag
    2.
    发明授权
    Reduced dry etching lag 有权
    减少干蚀刻滞后

    公开(公告)号：US07094687B1

    公开(公告)日：2006-08-22

    申请号：US11071903

    申请日：2005-03-02

    申请人： Masaichi Eda

    发明人： Masaichi Eda

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76802

    摘要： A method of forming via structures between a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer is formed, and a dielectric layer is formed over the first electrically conductive layer. A first photoresist layer is formed over the dielectric layer, and patterned with a first via hole pattern. The first via hole pattern includes via holes that are all disposed within a first distance one from another, called dense via holes, and excludes via holes that are disposed at greater than the first distance one from another, called isolated via holes. The dense via holes are etched into the dielectric layer at first etch conditions until the dense via holes are properly formed, and the first photoresist layer is removed. A second photoresist layer is formed over the dielectric layer, and is patterned with a second via hole pattern. The second via hole pattern excludes dense via holes and includes isolated via holes. The isolated via holes are etched into the dielectric layer at second etch conditions until the isolated via holes are properly formed, and the second photoresist layer is removed. Electrically conductive vias are formed within both the dense via holes and the isolated via holes, and the second electrically conductive layer is formed over the dielectric layer. Electrical continuity exists between the first electrically conductive layer and the second electrically conductive layer through the electrically conductive vias.

    摘要翻译： 一种在第一导电层和第二导电层之间形成通孔结构的方法。 形成第一导电层，并且在第一导电层上形成电介质层。 在电介质层上形成第一光致抗蚀剂层，并用第一通孔图案构图。 第一通孔图案包括通孔，所述通孔全部设置在彼此之间的第一距离内，称为密集通孔，并且不包括称为隔离通孔的大于第一距离的通孔。 在第一蚀刻条件下将密集的通孔蚀刻到电介质层中，直到适当地形成致密通孔，并且去除第一光致抗蚀剂层。 在电介质层上方形成第二光致抗蚀剂层，并用第二通孔图案构图。 第二通孔图案排除了密集的通孔，并且包括隔离的通孔。 隔离的通孔在第二蚀刻条件下蚀刻到电介质层中，直到隔离的通孔适当地形成，并且去除第二光致抗蚀剂层。 导电通孔形成在密集通孔和隔离通孔内，第二导电层形成在介电层上。 通过导电通孔在第一导电层和第二导电层之间存在电连续性。

    Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene process
    4.
    发明授权
    Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene process 有权
    用于减少在双镶嵌工艺中产生的无边界通孔的微切削的方法和装置

    公开(公告)号：US06794304B1

    公开(公告)日：2004-09-21

    申请号：US10631528

    申请日：2003-07-31

    申请人： Shiqun Gu ,  Masaichi Eda ,  Peter McGrath ,  Hong Lin ,  Jim Elmer

    发明人： Shiqun Gu ,  Masaichi Eda ,  Peter McGrath ,  Hong Lin ,  Jim Elmer

    IPC分类号： H01L21302

    CPC分类号： H01L21/76897 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76834

    摘要： A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. An upper surface of the second element slopes downwardly toward the upper surface of the first element. A first layer of a second substantially non-electrically conductive material is disposed over the upper surface of the first element and the upper surface of the second element. The first layer has a thickness in the vertical direction that is greater in an area over the downward slope of the second element than in an area over the first element. An etching process is performed such that the layer is perforated above the upper surface of the first element and imperforated in the vertically thicker area above the downwardly sloping upper surface of the second element.

    摘要翻译： 制造半导体器件的方法包括提供由第一基本上导电的材料形成并具有上表面的第一元件。 提供了与第一元件相邻的第二元件。 第二元件由第一基本上不导电的材料形成。 第二元件的上表面朝向第一元件的上表面向下倾斜。 第二基本上非导电材料的第一层设置在第一元件的上表面和第二元件的上表面之上。 第一层具有在垂直方向上的厚度，该厚度在第二元件的向下倾斜度上比在第一元件上的区域中大得多。 进行蚀刻处理，使得该层在第一元件的上表面上方穿孔，并且在第二元件的向下倾斜的上表面上方的垂直较厚的区域中无孔。

    REDUCED DRY ETCHING LAG
    5.
    发明申请
    REDUCED DRY ETCHING LAG 有权
    减少干ING ING

    公开(公告)号：US20060199366A1

    公开(公告)日：2006-09-07

    申请号：US11071903

    申请日：2005-03-02

    申请人： Masaichi Eda

    发明人： Masaichi Eda

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76802

    摘要： A method of forming via structures between a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer is formed, and a dielectric layer is formed over the first electrically conductive layer. A first photoresist layer is formed over the dielectric layer, and patterned with a first via hole pattern. The first via hole pattern includes via holes that are all disposed within a first distance one from another, called dense via holes, and excludes via holes that are disposed at greater than the first distance one from another, called isolated via holes. The dense via holes are etched into the dielectric layer at first etch conditions until the dense via holes are properly formed, and the first photoresist layer is removed. A second photoresist layer is formed over the dielectric layer, and is patterned with a second via hole pattern. The second via hole pattern excludes dense via holes and includes isolated via holes. The isolated via holes are etched into the dielectric layer at second etch conditions until the isolated via holes are properly formed, and the second photoresist layer is removed. Electrically conductive vias are formed within both the dense via holes and the isolated via holes, and the second electrically conductive layer is formed over the dielectric layer. Electrical continuity exists between the first electrically conductive layer and the second electrically conductive layer through the electrically conductive vias.

    摘要翻译： 一种在第一导电层和第二导电层之间形成通孔结构的方法。 形成第一导电层，并且在第一导电层上形成电介质层。 在电介质层上形成第一光致抗蚀剂层，并用第一通孔图案构图。 第一通孔图案包括通孔，所述通孔全部设置在彼此之间的第一距离内，称为密集通孔，并且不包括称为隔离通孔的大于第一距离的通孔。 在第一蚀刻条件下将密集的通孔蚀刻到电介质层中，直到适当地形成致密通孔，并且去除第一光致抗蚀剂层。 在电介质层上方形成第二光致抗蚀剂层，并用第二通孔图案构图。 第二通孔图案排除了密集的通孔，并且包括隔离的通孔。 隔离的通孔在第二蚀刻条件下蚀刻到电介质层中，直到隔离的通孔适当地形成，并且去除第二光致抗蚀剂层。 导电通孔形成在密集通孔和隔离通孔内，第二导电层形成在介电层上。 通过导电通孔在第一导电层和第二导电层之间存在电连续性。

    High selectivity SiC etch in integrated circuit fabrication
    6.
    发明授权
    High selectivity SiC etch in integrated circuit fabrication 有权
    集成电路制造中的高选择性SiC蚀刻

    公开(公告)号：US06743725B1

    公开(公告)日：2004-06-01

    申请号：US09928570

    申请日：2001-08-13

    申请人： Rongxiang Hu ,  Philippe Schoenborn ,  Masaichi Eda

    发明人： Rongxiang Hu ,  Philippe Schoenborn ,  Masaichi Eda

    IPC分类号： H01L21311

    CPC分类号： C09K13/00 ,  C09K13/08 ,  H01L21/31116 ,  H01L21/76807

    摘要： The subject matter described herein involves an improved etch process for use in fabricating integrated circuits on semiconductor wafers. The selectivity of the etch process for silicon carbide versus silicon oxide, organo silica-glass or other low dielectric constant type material is enhanced by adding hydrogen (H2) or ammonia (NH3) or other hydrogen-containing gas to the etch chemistry.

    摘要翻译： 本文描述的主题涉及用于制造半导体晶片上的集成电路的改进的蚀刻工艺。 碳化硅与氧化硅，有机二氧化硅玻璃或其他低介电常数型材料的蚀刻工艺的选择性通过向蚀刻化学品中加入氢（H 2）或氨（NH 3）或其它含氢气体来增强。