公开(公告)号：US5549934A

公开(公告)日：1996-08-27

申请号：US462651

申请日：1995-06-05

申请人： Mario Garza ,  Keith Chao

发明人： Mario Garza ,  Keith Chao

IPC分类号： C08G77/12 ,  C09D183/04 ,  C23C18/12 ,  H01L21/316 ,  C08J7/18

CPC分类号： H01L21/316 ,  C08G77/12 ,  C09D183/04 ,  C23C18/1212 ,  C23C18/122

摘要： A process is disclosed for curing a hydrogen silsesquioxane coating material to form SiO.sub.2 by first placing the coating material in a preheated furnace; igniting a plasma ignited in the furnace immediately after insertion of the coating material therein; then raising the temperature of the furnace up to a predetermined curing temperature, while still maintaining the plasma in the chamber; maintaining the coating material at the curing temperature until substantially all of the coating material has cured to form SiO.sub.2 ; and then extinguishing the plasma and cooling the furnace. In another embodiment, the coating material is cured, with or without the assistance of heat and a plasma, in an ultrahigh vacuum, i.e., a vacuum of at least 10.sup.-5 Torr or better, and preferably at least 10.sup.-6 Torr or better.

公开(公告)号：US06713386B1

公开(公告)日：2004-03-30

申请号：US10025304

申请日：2001-12-19

申请人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

发明人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76826 ,  H01L21/76829

摘要： A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

公开(公告)号：US6109775A

公开(公告)日：2000-08-29

申请号：US925021

申请日：1997-09-08

申请人： Prabhakar P. Tripathi ,  Keith Chao ,  Ratan K. Choudhury ,  Gauri C. Das ,  Nicholas K. Eib ,  Ashok K. Kapoor ,  Thomas G. Mallon

发明人： Prabhakar P. Tripathi ,  Keith Chao ,  Ratan K. Choudhury ,  Gauri C. Das ,  Nicholas K. Eib ,  Ashok K. Kapoor ,  Thomas G. Mallon

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  G06F17/00 ,  G06F17/50

CPC分类号： H01L21/76838 ,  H01L21/31053 ,  H01L21/76816 ,  H01L21/76819 ,  H01L23/522 ,  H01L2924/0002

摘要： Disclosed is the formation of additional lines, either dummy lines or active lines, in an electrically conductive pattern of lines to provide more uniform loading for either etching or chemical/mechanical polishing of a layer of electrically conductive material from which the pattern of lines is formed. Also disclosed is the use of additional or dummy vias to balance the loading during etching of the vias, as well as to provide stress relief for underlying metal in regions or areas having a low density of vias. Further disclosed is the use of a working grid on the integrated circuit structure to analyze the spacing of lines or vias for the above effects.

摘要翻译： 公开了在导电图案线中形成额外的线，虚拟线或有源线，以提供更均匀的负载，用于蚀刻或化学/机械抛光一层导电材料，从其形成线图案 。 还公开了使用额外的或虚拟的通孔来平衡通孔蚀刻期间的负载，以及为具有低密度通孔的区域或区域中的下面的金属提供应力释放。 还公开了在集成电路结构上使用工作网格以分析上述效应的线或通孔的间隔。

公开(公告)号：US5663017A

公开(公告)日：1997-09-02

申请号：US477827

申请日：1995-06-07

申请人： Richard Schinella ,  Keith Chao

发明人： Richard Schinella ,  Keith Chao

IPC分类号： G03F7/20 ,  G03F9/00

CPC分类号： G03F7/70441 ,  G03F7/70475

摘要： Method and apparatus for forming large scale fields suitable for use in the fabrication of integrated circuit structures having submicron dimensions. The method includes subdividing the large scale field into a plurality of subfields along the boundaries of functional components forming a very large scale integrated circuit. Stitching the subfields into the large scale field is then substantially simplified since the number and dimensions of conductive interconnects between the functional components can be more easily accommodated. The large scale field further includes a custom portion and a standard portion of functional components. Reticle formation of the standard portion involves optical correction techniques. Reticle formation of the custom portion may involve standard reticle formation techniques.

摘要翻译： 用于形成适合用于制造具有亚微米尺寸的集成电路结构的大规模场的方法和装置。 该方法包括沿着形成非常大规模集成电路的功能部件的边界将大尺度场细分为多个子场。 因此，可以更容易地容纳功能部件之间的导电互连的数量和尺寸，从而将子场拼接成大规模场。 大规模场还包括定制部分和功能部件的标准部分。 标准部分的标线形成涉及光学校正技术。 定制部分的标线形成可以包括标准的掩模版形成技术。

公开(公告)号：US5652163A

公开(公告)日：1997-07-29

申请号：US357728

申请日：1994-12-13

申请人： Richard D. Schinella ,  Keith Chao

发明人： Richard D. Schinella ,  Keith Chao

IPC分类号： G03F7/20 ,  H01L27/02 ,  H01L21/82

CPC分类号： G03F7/70466 ,  G03F7/70433 ,  H01L27/0207

摘要： A method and apparatus for forming large scale fields suitable for use in the fabrication of integrated circuit structures having submicron dimensions. The method includes subdividing the large scale field into a plurality of subfields along the boundaries of functional components forming a very large scale integrated circuit. Stitching the subfields into the large scale field is then substantially simplified since the number and dimensions of conductive interconnects between the functional components can be more easily accommodated.

摘要翻译： 一种用于形成适用于制造具有亚微米尺寸的集成电路结构的大规模场的方法和装置。 该方法包括沿着形成非常大规模集成电路的功能部件的边界将大尺度场细分为多个子场。 因此，可以更容易地容纳功能部件之间的导电互连的数量和尺寸，从而将子场拼接成大规模场。

公开(公告)号：US06969683B2

公开(公告)日：2005-11-29

申请号：US10750348

申请日：2003-12-31

申请人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

发明人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

IPC分类号： H01L21/311 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76831 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76826 ,  H01L21/76829

摘要： A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

摘要翻译： 提供了一种在电介质层中形成双镶嵌互连的方法。 通常，在电介质中蚀刻第一孔。 在电介质的一部分上形成中毒阻挡层，防止抗蚀剂中毒。 在毒物屏障层上形成图案化掩模。 第二孔被蚀刻到电介质层中，其中第一孔的至少一部分具有与第二孔的至少一部分相同的面积。

公开(公告)号：US5456952A

公开(公告)日：1995-10-10

申请号：US245191

申请日：1994-05-17

申请人： Mario Garza ,  Keith Chao

发明人： Mario Garza ,  Keith Chao

IPC分类号： C08G77/12 ,  C09D183/04 ,  C23C18/12 ,  H01L21/316 ,  B05D1/00 ,  B05D3/02

CPC分类号： H01L21/316 ,  C08G77/12 ,  C09D183/04 ,  C23C18/1212 ,  C23C18/122

摘要： A process is disclosed for curing a hydrogen silsesquioxane coating material to form SiO.sub.2 by first placing the coating material in a preheated furnace; igniting a plasma ignited in the furnace immediately after insertion of the coating material therein; then raising the temperature of the furnace up to a predetermined curing temperature, while still maintaining the plasma in the chamber; maintaining the coating material at the curing temperature until substantially all of the coating material has cured to form SiO.sub.2 ; and then extinguishing the plasma and cooling the furnace. In another embodiment, the coating material is cured, with or without the assistance of heat and a plasma, in an ultrahigh vacuum, i.e., a vacuum of at least 10.sup.-5 Torr or better, and preferably at least 10.sup.-6 Torr or better.

摘要翻译： 公开了一种通过首先将涂层材料放置在预热炉中来固化氢倍半硅氧烷涂层材料以形成SiO 2的方法; 点燃在其中插入涂料后立即在炉中点燃的等离子体; 然后将炉子的温度提高到预定的固化温度，同时仍然将等离子体保持在室中; 将涂料保持在固化温度，直到基本上所有的涂料固化形成SiO 2; 然后熄灭等离子体并冷却炉。 在另一个实施方案中，涂层材料在超高真空下即有或几何以上，优选至少为10 -6 Torr或更好的真空中，有或没有热和等离子体的帮助而被固化 。