摘要:
A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.
摘要:
A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.
摘要:
Protective caps are formed over horizontally closely spaced apart metal lines of an integrated circuit structure. Low k silicon oxide dielectric material is then deposited over and between the metal lines and over protective caps on the lines. After the formation of such low k material between the lines and over the caps, standard k dielectric material is deposited over the low k layer as a planarizing layer over low portions of the low k layer between the lines which may be lower than the top of the caps on the lines to prevent further etching or dishing of the low k layer of during planarizing. The structure is then planarized to bring the low k dielectric material down to the tops of the protective caps on the metal lines. A layer of standard k silicon material is then formed over the planarized low k layer and the caps to allow via formation without passing through the low k layer to avoid via poisoning.
摘要:
A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus. The substrate is then solvent cleaned to remove etch residues and then annealed to degasify the low k dielectric material. The substrate is then RF cleaned and a thin layer of PVD titanium is then formed in the same chamber over the surfaces of the openings. CVD titanium nitride is then formed over the titanium in the same vacuum apparatus. The coated openings are then filled with aluminum, tungsten, or copper.
摘要:
Via poisoning of vias formed in low k carbon-containing silicon oxide dielectric material is suppressed by forming the via in a layer of such dielectric material with a smooth inwardly sloped sidewall. Such a sloped sidewall via can be etched in a low k dielectric layer by first forming a via resist mask over the upper surface of such a dielectric layer, then heat treating the mask sufficiently to deform the sidewall geometry of the resist mask to form a sloped sidewall on the opening or openings in the heat treated resist mask. The resulting erosion of such a resist mask, during a subsequent etch step to form the via in the low k dielectric material through such a sloped sidewall resist mask, imparts a tapered or sloped sidewall geometry to the via which is then formed in the underlying layer of low k dielectric material. In a preferred embodiment, when the via is cut through several layers of different types of dielectric material, the smoothness of the sloped sidewall of the resulting via is enhanced by adjusting the selectivity of the via etch to uniformly etch each of the layers of dielectric material at approximately the same rate.
摘要:
A method and apparatus for adaptive de-blocking filter are disclosed. One or more parameters associated with a de-blocking filter are determined. De-blocking filter using the derived parameters are then applied to reconstructed blocks. Each set of parameters is used for each picture, slice, coding tree unit (CTU) or CU (coding unit). The parameters can be signalled in VPS (video parameter set), SPS (sequence parameter set), PPS (picture parameter set), slice header, CTU (coding tree unit) or CU (coding unit) of the video bitstream. The parameters correspond to one or more values used as thresholds, clipping boundaries, or both the thresholds and clipping boundaries for the de-blocking filter. In one embodiment, the parameters for the current picture are determined using a training process using a current coded picture a previous coded picture as training data.
摘要:
Improvements in a bracket is disclosed for mounting an electrical box onto a mounting bar. An electrical box can be preinstalled onto the bracket and clamped onto the mounting bar using wings. Bendable tabs can be articulated to secure the bracket and onto a rail. Fasteners are used to secure an electrical junction box onto the bracket and an additional fastener secures the sub assembly to the rail. The tabs can be unbent for removal. An installer can secure the bracket and electrical box using a screw and adjust the position of the bracket on the mounting bar. The bracket provides a low profile assemble that allows the bracket to be installed between the inner surfaces of stud walls.
摘要:
According to the invention, generally, a microfluidic aliquoting (MA) chip, adapted to fit in a Petri dish, has a center well (inlet) connected by branched channels to a plurality of side wells (outlets). The chip comes in various types, including a bMA Chip T1, bMA Chip T2, bMA Chip T3, and an rMA Chip. The branched channel improvement provides for a greater distance between neighboring channels and a decreased density near the center well. Design improvements including an injection mold design for an insert and a base and a multiplex hole punch allow for rapid fabrication of the MA chip.