公开(公告)号：US20090289659A1

公开(公告)日：2009-11-26

申请号：US12453730

申请日：2009-05-20

申请人： Shunji Kuwahara ,  Hiroki Fujisawa

发明人： Shunji Kuwahara ,  Hiroki Fujisawa

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/022 ,  G11C29/028

摘要： In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLK1 to both a hit determination circuit and a second clock gate circuit. The second clock gate circuit 110 passes through the first update clocks CLK1 until reception of a hit signal from the hit determination circuit and delivers second update clocks CLK2 to an up/down counter 106. The up/down counter 106 is operated by the second update clocks CLK2. With this structure, the second update clocks used for adjustment steps can be increased in number during the calibration period.

摘要翻译： 在校准控制电路中，第一时钟门电路在校准周期期间限制参考更新时钟的通过，以停止参考更新时钟中的第一个，并将限制参考更新时钟作为第一更新时钟CLK1提供给命中确定 电路和第二时钟门电路。 第二时钟门电路110通过第一更新时钟CLK1直到从命中确定电路接收到命中信号，并将第二更新时钟CLK2递送到升/降计数器106.升/减计数器106由第二更新 时钟CLK2。 利用这种结构，在校准期间可以增加用于调整步骤的第二更新时钟的数量。

公开(公告)号：US09041436B2

公开(公告)日：2015-05-26

申请号：US13317696

申请日：2011-10-26

申请人： Shunji Kuwahara ,  Hiroki Fujisawa

发明人： Shunji Kuwahara ,  Hiroki Fujisawa

IPC分类号： H03K3/00 ,  G11C11/4074 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4093

CPC分类号： G11C11/4074 ,  G11C5/063 ,  G11C7/1057 ,  G11C11/4093 ,  Y10T307/50

摘要： To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.

摘要翻译： 为了减少用于控制输出缓冲器的控制电路单元中发生的电源噪声。 半导体器件包括用于驱动数据输出端子的单元缓冲器，用于控制单元缓冲器的阻抗控制电路，以及用于控制阻抗控制电路的控制电路单元。 阻抗控制电路和控制电路单元通过相互不同的电源进行工作，控制电路单元向阻抗控制电路提供相互反相的上拉数据和下拉数据，并且阻抗控制电路将拉 - 并将下拉数据从反相到同相，并将其提供给单元缓冲器。 因此，在用于控制电路单元的电源VDD中难以发生噪声。

公开(公告)号：US08278973B2

公开(公告)日：2012-10-02

申请号：US12707354

申请日：2010-02-17

申请人： Shunji Kuwahara ,  Hiroki Fujisawa

发明人： Shunji Kuwahara ,  Hiroki Fujisawa

IPC分类号： H03B1/00

CPC分类号： H03K19/017581 ,  H03K19/0005

摘要： To include two counter circuits that change impedances of two replica circuits, respectively, and an impedance adjustment control circuit that controls the counter circuits to update count values of the counter circuits. The impedance adjustment control circuit controls one of the counter circuits to finish updating the count value of the counter circuit in response to a change of the impedance of the corresponding replica circuit from a state of being lower than an impedance of an external resistor to a state of being higher than the impedance of the external resistor, and controls the other counter circuit to finish updating the count value of the other counter circuit in response to a change of the impedance of the other replica circuit from a state of being higher than the impedance of the former replica circuit to a state of being lower than the impedance of the former replica circuit. With this configuration, the adjust errors generated in the replica circuits are canceled.

摘要翻译： 包括分别改变两个复制电路的阻抗的两个计数器电路以及控制计数器电路来更新计数器电路的计数值的阻抗调整控制电路。 阻抗调整控制电路控制其中一个计数器电路，以响应于相应的复制电路的阻抗从低于外部电阻器的阻抗的状态改变到状态来完成对计数器电路的计数值的更新 高于外部电阻器的阻抗，并且响应于另一个复制电路的阻抗从高于阻抗的状态改变而控制另一个计数器电路来完成另一个计数器电路的计数值的更新 的原始复制电路的状态低于前一复制电路的阻抗。 利用这种配置，复制电路中产生的调整错误被取消。

公开(公告)号：US20110062984A1

公开(公告)日：2011-03-17

申请号：US12923249

申请日：2010-09-10

申请人： Shunji Kuwahara ,  Hiroki Fujisawa

发明人： Shunji Kuwahara ,  Hiroki Fujisawa

IPC分类号： H03K19/003 ,  H03K19/094

CPC分类号： H03K19/0005 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2254

摘要： To include an output terminal, unit buffers, and plural output-wiring paths that respectively connect the unit buffers and the output terminal. The output wiring paths have individual output wiring sections individually allocated to corresponding unit buffers. Unit buffers corresponding to these output wiring paths are common output wiring sections shared by the output wiring paths, and are connected to the output terminal without via a common output wiring section having a higher resistance value than those of the individual output wiring sections. Accordingly, an deviation of impedance due to a parasitic resistance between the output terminal and the unit buffers is suppressed.

摘要翻译： 包括分别连接单元缓冲器和输出端子的输出端子，单元缓冲器和多个输出布线路径。 输出布线路径具有分别分配给相应单元缓冲器的各个输出布线部分。 对应于这些输出布线路径的单元缓冲器是由输出布线路径共享的公共输出布线部分，并且不经由具有比各个输出布线部分的电阻值高的公共输出布线部分连接到输出端子。 因此，抑制了由于输出端子和单元缓冲器之间的寄生电阻引起的阻抗的偏差。

公开(公告)号：US07902858B2

公开(公告)日：2011-03-08

申请号：US12216676

申请日：2008-07-09

申请人： Shunji Kuwahara ,  Hiroki Fujisawa

发明人： Shunji Kuwahara ,  Hiroki Fujisawa

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K5/12

CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C29/022 ,  G11C29/50008 ,  G11C2207/2254 ,  H01L2924/0002 ,  H01L2924/00

摘要： A calibration circuit includes: a replica buffer that drives a calibration terminal; a pre-emphasis circuit connected in parallel to the replica buffer; and an up-down counter that changes impedances of the replica buffer and the pre-emphasis circuit. A replica control circuit causes the replica buffer to conduct based on an impedance code, and a pre-emphasis control circuit causes the pre-emphasis circuit to conduct in an initial stage of a conducting period of the replica buffer. Thereby, even when an external resistor is shared among a plurality of semiconductor devices, for example, a voltage appearing in the calibration terminal can be stabilized at a higher speed.

摘要翻译： 校准电路包括：驱动校准终端的副本缓冲器; 与复制缓冲器并联连接的预加重电路; 以及改变复制缓冲器和预加重电路的阻抗的升降计数器。 复制控制电路使得复制缓冲器基于阻抗代码进行，并且预加重控制电路使预加重电路在复制缓冲器的导通周期的初始阶段中进行。 因此，即使在多个半导体器件中共享外部电阻器的情况下，例如也可以以更高的速度稳定校准端子中出现的电压。

公开(公告)号：US07872493B2

公开(公告)日：2011-01-18

申请号：US12453730

申请日：2009-05-20

申请人： Shunji Kuwahara ,  Hiroki Fujisawa

发明人： Shunji Kuwahara ,  Hiroki Fujisawa

IPC分类号： H03K19/003

CPC分类号： H03K19/0005 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/022 ,  G11C29/028

摘要： In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLK1 to both a hit determination circuit and a second clock gate circuit. The second clock gate circuit 110 passes through the first update clocks CLK1 until reception of a hit signal from the hit determination circuit and delivers second update clocks CLK2 to an up/down counter 106. The up/down counter 106 is operated by the second update clocks CLK2. With this structure, the second update clocks used for adjustment steps can be increased in number during the calibration period.

摘要翻译： 在校准控制电路中，第一时钟门电路在校准周期期间限制参考更新时钟的通过，以停止参考更新时钟中的第一个，并将限制参考更新时钟作为第一更新时钟CLK1提供给命中确定 电路和第二时钟门电路。 第二时钟门电路110通过第一更新时钟CLK1直到从命中确定电路接收到命中信号，并将第二更新时钟CLK2传送到升/降计数器106.升/减计数器106由第二更新 时钟CLK2。 利用这种结构，在校准期间可以增加用于调整步骤的第二更新时钟的数量。

公开(公告)号：US08461867B2

公开(公告)日：2013-06-11

申请号：US12923249

申请日：2010-09-10

申请人： Shunji Kuwahara ,  Hiroki Fujisawa

发明人： Shunji Kuwahara ,  Hiroki Fujisawa

IPC分类号： H03K17/16 ,  H01L25/00

CPC分类号： H03K19/0005 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2254

摘要： To include an output terminal, unit buffers, and plural output-wiring paths that respectively connect the unit buffers and the output terminal. The output wiring paths have individual output wiring sections individually allocated to corresponding unit buffers. Unit buffers corresponding to these output wiring paths are common output wiring sections shared by the output wiring paths, and are connected to the output terminal without via a common output wiring section having a higher resistance value than those of the individual output wiring sections. Accordingly, an deviation of impedance due to a parasitic resistance between the output terminal and the unit buffers is suppressed.

摘要翻译： 包括分别连接单元缓冲器和输出端子的输出端子，单元缓冲器和多个输出布线路径。 输出布线路径具有分别分配给相应单元缓冲器的各个输出布线部分。 对应于这些输出布线路径的单元缓冲器是由输出布线路径共享的公共输出布线部分，并且不经由具有比各个输出布线部分的电阻值高的公共输出布线部分连接到输出端子。 因此，抑制了由于输出端子和单元缓冲器之间的寄生电阻引起的阻抗的偏差。

公开(公告)号：US20100207680A1

公开(公告)日：2010-08-19

申请号：US12707354

申请日：2010-02-17

申请人： Shunji KUWAHARA ,  Hiroki FUJISAWA

发明人： Shunji KUWAHARA ,  Hiroki FUJISAWA

IPC分类号： G05F3/00

CPC分类号： H03K19/017581 ,  H03K19/0005

摘要： To include two counter circuits that change impedances of two replica circuits, respectively, and an impedance adjustment control circuit that controls the counter circuits to update count values of the counter circuits. The impedance adjustment control circuit controls one of the counter circuits to finish updating the count value of the counter circuit in response to a change of the impedance of the corresponding replica circuit from a state of being lower than an impedance of an external resistor to a state of being higher than the impedance of the external resistor, and controls the other counter circuit to finish updating the count value of the other counter circuit in response to a change of the impedance of the other replica circuit from a state of being higher than the impedance of the former replica circuit to a state of being lower than the impedance of the former replica circuit. With this configuration, the adjust errors generated in the replica circuits are canceled.

摘要翻译： 包括分别改变两个复制电路的阻抗的两个计数器电路以及控制计数器电路来更新计数器电路的计数值的阻抗调整控制电路。 阻抗调整控制电路控制其中一个计数器电路，以响应于相应的复制电路的阻抗从低于外部电阻器的阻抗的状态改变到状态来完成对计数器电路的计数值的更新 高于外部电阻器的阻抗，并且响应于另一个复制电路的阻抗从高于阻抗的状态改变而控制另一个计数器电路来完成另一个计数器电路的计数值的更新 的原始复制电路的状态低于前一复制电路的阻抗。 利用这种配置，复制电路中产生的调整错误被取消。

公开(公告)号：US20090015312A1

公开(公告)日：2009-01-15

申请号：US12216676

申请日：2008-07-09

申请人： Shunji Kuwahara ,  Hiroki Fujisawa

发明人： Shunji Kuwahara ,  Hiroki Fujisawa

IPC分类号： H03L5/00

CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C29/022 ,  G11C29/50008 ,  G11C2207/2254 ,  H01L2924/0002 ,  H01L2924/00

摘要： A calibration circuit includes: a replica buffer that drives a calibration terminal; a pre-emphasis circuit connected in parallel to the replica buffer; and an up-down counter that changes impedances of the replica buffer and the pre-emphasis circuit. A replica control circuit causes the replica buffer to conduct based on an impedance code, and a pre-emphasis control circuit causes the pre-emphasis circuit to conduct in an initial stage of a conducting period of the replica buffer. Thereby, even when an external resistor is shared among a plurality of semiconductor devices, for example, a voltage appearing in the calibration terminal can be stabilized at a higher speed.

摘要翻译： 校准电路包括：驱动校准终端的副本缓冲器; 与复制缓冲器并联连接的预加重电路; 以及改变复制缓冲器和预加重电路的阻抗的升降计数器。 复制控制电路使得复制缓冲器基于阻抗代码进行，并且预加重控制电路使预加重电路在复制缓冲器的导通周期的初始阶段中进行。 因此，即使在多个半导体器件中共享外部电阻器的情况下，例如也可以以更高的速度稳定校准端子中出现的电压。

公开(公告)号：US20120119578A1

公开(公告)日：2012-05-17

申请号：US13317696

申请日：2011-10-26

申请人： Shunji Kuwahara ,  Hiroki Fujisawa

发明人： Shunji Kuwahara ,  Hiroki Fujisawa

IPC分类号： H02J1/00

CPC分类号： G11C11/4074 ,  G11C5/063 ,  G11C7/1057 ,  G11C11/4093 ,  Y10T307/50

摘要： To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.

摘要翻译： 为了减少用于控制输出缓冲器的控制电路单元中发生的电源噪声。 半导体器件包括用于驱动数据输出端子的单元缓冲器，用于控制单元缓冲器的阻抗控制电路，以及用于控制阻抗控制电路的控制电路单元。 阻抗控制电路和控制电路单元通过相互不同的电源进行工作，控制电路单元向阻抗控制电路提供相互反相的上拉数据和下拉数据，并且阻抗控制电路将拉 - 并将下拉数据从反相到同相，并将其提供给单元缓冲器。 因此，在用于控制电路单元的电源VDD中难以发生噪声。