公开(公告)号：US20080163023A1

公开(公告)日：2008-07-03

申请号：US11785719

申请日：2007-04-19

申请人： Si-Hoon Hong ,  Yun-Tae Lee ,  Jun-Jin Kong

发明人： Si-Hoon Hong ,  Yun-Tae Lee ,  Jun-Jin Kong

IPC分类号： H03M13/00

CPC分类号： H03M13/2945 ,  G06F11/1072 ,  H03M13/09 ,  H03M13/136 ,  H03M13/1505 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/29 ,  H03M13/2906

摘要： An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

摘要翻译： 存储M位数据（M为等于或大于2的正整数）的闪速存储器件的ECC（纠错码）控制器包括从程序数据生成第一ECC数据的第一ECC块， 根据第一纠错方法存储在闪速存储装置中的第二ECC数据和根据第二纠错方法从第一ECC数据和从第一ECC块输出的程序数据生成第二ECC数据的第二ECC块， ，第一ECC数据和第二ECC数据被存储在闪存设备中。

公开(公告)号：US20080151621A1

公开(公告)日：2008-06-26

申请号：US11802656

申请日：2007-05-24

申请人： Jun Jin Kong ,  Sung Chung Park ,  Dong Ku Kang ,  Young Hwan Lee ,  Si Hoon Hong ,  Jae Woong Hyun

发明人： Jun Jin Kong ,  Sung Chung Park ,  Dong Ku Kang ,  Young Hwan Lee ,  Si Hoon Hong ,  Jae Woong Hyun

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483

摘要： A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.

摘要翻译： 多级单元（MLC）存储器件可以包括“a”个m位MLC存储器单元; 编码器，其以k / n的码率对“k”位数据进行编码，以产生编码比特流; 以及信号映射模块，其向MLC存储器单元施加脉冲以便将编码比特流写入MLC存储器单元。 在设备中，'a'和'm'可以是大于或等于2的整数，'k'和'n'可以是大于或等于1的整数，'n'可能大于'k'。 在设备中存储数据的方法可以包括以k / n的码率对'k'位数据进行编码，以产生编码比特流。 从设备读取数据的方法可以包括以n / k的码率对'n'比特的数据进行解码，以产生解码比特流。

公开(公告)号：US20060294306A1

公开(公告)日：2006-12-28

申请号：US11511027

申请日：2006-08-28

申请人： Si-Hoon Hong

发明人： Si-Hoon Hong

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F3/0653 ,  G06F3/0605 ,  G06F3/0679 ,  G06F3/14 ,  G06F13/385

摘要： A USB flash memory device connected to a USB bus includes a flash memory module including at least one flash memory, a USB connector for transferring data packets onto the USB bus and receiving the data packets from the USB bus, a USB controller for controlling the USB connector according to the data packets and for controlling storage of data in and retrieval of data from the flash memory module, a display controller for storing memory storage capacity information of the flash memory module in a usage display register, a display window for displaying a value that is based on the content of the usage display register, and a power unit for supplying a power to the USB flash memory device. The USB connector is configured to be coupled to the USB bus. The USB flash memory device further includes a folding portion which is proximal to the USB connector and enables the USB flash memory device to be folded. According to the present invention, data storage information of the USB flash memory device and additional information such as current time and data storage time can be visually determined through the display window, even in cases where the USB flash memory device is not coupled to the host platform. Further, the folding portion of the USB flash memory device enhances space usability and efficiency.

公开(公告)号：US07124238B2

公开(公告)日：2006-10-17

申请号：US10737148

申请日：2003-12-16

申请人： Si-Hoon Hong

发明人： Si-Hoon Hong

IPC分类号： G06F12/00

CPC分类号： G06F3/0653 ,  G06F3/0605 ,  G06F3/0679 ,  G06F3/14 ,  G06F13/385

摘要： A USB flash memory device connected to a USB bus includes a flash memory module including at least one flash memory, a USB connector for transferring data packets onto the USB bus and receiving the data packets from the USB bus, a USB controller for controlling the USB connector according to the data packets and for controlling storage of data in and retrieval of data from the flash memory module, a display controller for storing memory storage capacity information of the flash memory module in a usage display register, a display window for displaying a value that is based on the content of the usage display register, and a power unit for supplying a power to the USB flash memory device. The USB connector is configured to be coupled to the USB bus. The USB flash memory device further includes a folding portion which is proximal to the USB connector and enables the USB flash memory device to be folded. According to the present invention, data storage information of the USB flash memory device and additional information such as current time and data storage time can be visually determined through the display window, even in cases where the USB flash memory device is not coupled to the host platform. Further, the folding portion of the USB flash memory device enhances space usability and efficiency.

公开(公告)号：US08539143B2

公开(公告)日：2013-09-17

申请号：US13421964

申请日：2012-03-16

申请人： Jin-Hyeok Choi ,  Sung-Hoon Lee ,  Si-Hoon Hong ,  Tae-Keun Jeon

发明人： Jin-Hyeok Choi ,  Sung-Hoon Lee ,  Si-Hoon Hong ,  Tae-Keun Jeon

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0646

摘要： A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access each memory card using the default RCA, and to change the default RCA to a unique RCA upon each sequential access.

摘要翻译： 提供了一种存储器系统，包括主处理器和连接到主处理器的多个级联连接的存储卡。 每个存储卡在存储器系统的初始化之前存储相同的默认相对卡地址（RCA）。 主处理器配置为使用默认RCA顺序访问每个存储卡，并且在每次顺序访问时将默认RCA更改为唯一的RCA。

公开(公告)号：US08499215B2

公开(公告)日：2013-07-30

申请号：US11802656

申请日：2007-05-24

申请人： Jun Jin Kong ,  Sung Chung Park ,  Dong Ku Kang ,  Young Hwan Lee ,  Si Hoon Hong ,  Jae Woong Hyun

发明人： Jun Jin Kong ,  Sung Chung Park ,  Dong Ku Kang ,  Young Hwan Lee ,  Si Hoon Hong ,  Jae Woong Hyun

IPC分类号： H03M13/29 ,  G11C29/00

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483

摘要： A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.

摘要翻译： 多级单元（MLC）存储器件可以包括“a”个m位MLC存储器单元; 编码器，其以k / n的码率对“k”位数据进行编码，以产生编码比特流; 以及信号映射模块，其向MLC存储器单元施加脉冲以便将编码比特流写入MLC存储器单元。 在设备中，'a'和'm'可以是大于或等于2的整数，'k'和'n'可以是大于或等于1的整数，'n'可能大于'k'。 在设备中存储数据的方法可以包括以k / n的码率对'k'位数据进行编码，以产生编码比特流。 从设备读取数据的方法可以包括以n / k的码率对'n'比特的数据进行解码，以产生解码比特流。

公开(公告)号：US20080175065A1

公开(公告)日：2008-07-24

申请号：US11875317

申请日：2007-10-19

申请人： Sung-Up Choi ,  Sung-Kook Bang ,  Si-Hoon Hong

发明人： Sung-Up Choi ,  Sung-Kook Bang ,  Si-Hoon Hong

IPC分类号： G11C11/34 ,  G06F12/00 ,  G11C7/10

CPC分类号： G11C16/102 ,  G11C8/06 ,  G11C16/105

摘要： A method of operating a non-volatile memory can include backing-up first data successfully programmed to a first target page of a non-volatile memory to provide local back-up data. A determination can be made that programming of second data to the first target page has failed and the local back-up data can be programmed to a second target page in a second block of the non-volatile memory.

摘要翻译： 操作非易失性存储器的方法可以包括备份成功编程到非易失性存储器的第一目标页面上的第一数据，以提供本地备份数据。 可以确定第二数据到第一目标页面的编程失败并且本地备份数据可以被编程到非易失性存储器的第二块中的第二目标页面。

公开(公告)号：US20080016276A1

公开(公告)日：2008-01-17

申请号：US11776243

申请日：2007-07-11

申请人： Si-Hoon Hong

发明人： Si-Hoon Hong

IPC分类号： G06F12/00

CPC分类号： G06F3/0653 ,  G06F3/0605 ,  G06F3/0679 ,  G06F3/14 ,  G06F13/385

摘要： A USB flash memory device connected to a USB bus includes a flash memory module including at least one flash memory, a USB connector for transferring data packets onto the USB bus and receiving the data packets from the USB bus, a USB controller for controlling the USB connector according to the data packets and for controlling storage of data in and retrieval of data from the flash memory module, a display controller for storing memory storage capacity information of the flash memory module in a usage display register, a display window for displaying a value that is based on the content of the usage display register, and a power unit for supplying a power to the USB flash memory device. The USB connector is configured to be coupled to the USB bus. The USB flash memory device further includes a folding portion which is proximal to the USB connector and enables the USB flash memory device to be folded. According to the present invention, data storage information of the USB flash memory device and additional information such as current time and data storage time can be visually determined through the display window, even in cases where the USB flash memory device is not coupled to the host platform. Further, the folding portion of the USB flash memory device enhances space usability and efficiency.

摘要翻译： 连接到USB总线的USB闪存设备包括闪速存储器模块，其包括至少一个闪存，用于将数据分组传送到USB总线上并从USB总线接收数据分组的USB连接器，用于控制USB的USB控制器 连接器，用于控制来自闪存模块的数据的存储和数据的存储，用于在使用显示寄存器中存储闪存模块的存储器存储容量信息的显示控制器，用于显示值的显示窗口 其基于使用显示寄存器的内容，以及用于向USB闪存设备供电的电源单元。 USB连接器被配置为耦合到USB总线。 USB闪存设备还包括靠近USB连接器的折叠部分，并且使USB闪存设备能够被折叠。 根据本发明，即使在USB闪存设备未连接到主机的情况下，也可以通过显示窗口可视地确定USB闪存设备的数据存储信息和诸如当前时间和数据存储时间的附加信息 平台。 此外，USB闪存设备的折叠部分增强了空间的可用性和效率。

公开(公告)号：US20120179871A1

公开(公告)日：2012-07-12

申请号：US13421964

申请日：2012-03-16

申请人： Jin-Hyeok CHOI ,  Sung-Hoon LEE ,  Si-Hoon HONG ,  Tae-Keun JEON

发明人： Jin-Hyeok CHOI ,  Sung-Hoon LEE ,  Si-Hoon HONG ,  Tae-Keun JEON

IPC分类号： G06F12/00

CPC分类号： G06F12/0646

摘要： A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access each memory card using the default RCA, and to change the default RCA to a unique RCA upon each sequential access.

摘要翻译： 提供了一种存储器系统，包括主处理器和连接到主处理器的多个级联连接的存储卡。 每个存储卡在存储器系统的初始化之前存储相同的默认相对卡地址（RCA）。 主处理器配置为使用默认RCA顺序访问每个存储卡，并且在每次顺序访问时将默认RCA更改为唯一的RCA。

公开(公告)号：US08112689B2

公开(公告)日：2012-02-07

申请号：US11785719

申请日：2007-04-19

申请人： Si-Hoon Hong ,  Yun-Tae Lee ,  Jun-Jin Kong

发明人： Si-Hoon Hong ,  Yun-Tae Lee ,  Jun-Jin Kong

IPC分类号： H03M13/00

CPC分类号： H03M13/2945 ,  G06F11/1072 ,  H03M13/09 ,  H03M13/136 ,  H03M13/1505 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/29 ,  H03M13/2906

摘要： An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

摘要翻译： 存储M位数据（M为等于或大于2的正整数）的闪速存储器件的ECC（纠错码）控制器包括从程序数据生成第一ECC数据的第一ECC块， 根据第一纠错方法存储在闪速存储装置中的第二ECC数据和根据第二纠错方法从第一ECC数据和从第一ECC块输出的程序数据生成第二ECC数据的第二ECC块， ，第一ECC数据和第二ECC数据被存储在闪存设备中。