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    Non-volatile memory device including block state confirmation cell and method of operating the same
    1.
    发明申请
    Non-volatile memory device including block state confirmation cell and method of operating the same 审中-公开
    包括块状态确认单元的非易失性存储器件及其操作方法

    公开(公告)号：US20120026790A1

    公开(公告)日：2012-02-02

    申请号：US13137668

    申请日：2011-09-01

    申请人： Ju-hee Park ,  Jae-woong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

    发明人： Ju-hee Park ,  Jae-woong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

    IPC分类号： G11C16/10 ,  G11C16/06 ,  G11C16/04

    CPC分类号： G11C11/5642 ,  G11C2211/5641 ,  G11C2211/5646

    摘要： Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell.

    摘要翻译： 提供了具有块状态确认单元的半导体器件，其可以存储指示写入多个存储器单元的数据位数的信息，基于写入的数据位的数量读取存储器数据的方法和/或存储器 存储指示写入数据位数的信息的编程方法。 半导体器件可以包括一个或多个存储器块和控制器。 每个存储器块可以包括存储数据的多个存储单元，以及存储指示写入存储单元的数据位数的信息的块状态确认单元。 控制器可以基于在块状态确认单元中的信息中指示的数据位数来从存储器块读取数据位。

    Memory cell programming method and semiconductor device for simultaneously programming a plurality of memory block groups
    3.
    发明授权
    Memory cell programming method and semiconductor device for simultaneously programming a plurality of memory block groups 有权
    用于同时编程多个存储块组的存储单元编程方法和半导体器件

    公开(公告)号：US07911842B2

    公开(公告)日：2011-03-22

    申请号：US12081568

    申请日：2008-04-17

    申请人： Ju-hee Park ,  Jae-woong Hyun ,  Yoon-dong Park ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song ,  Jun-jin Kong ,  Sung-chung Park

    发明人： Ju-hee Park ,  Jae-woong Hyun ,  Yoon-dong Park ,  Kyoung-lae Cho ,  Sung-jae Byun ,  Seung-hwan Song ,  Jun-jin Kong ,  Sung-chung Park

    IPC分类号： G11C16/04

    CPC分类号： H01L29/7883 ,  G11C16/10

    摘要： Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an ith bit of the data may be simultaneously written to two or more memory block groups from among the plurality memory block groups, and then an i+1th bit of the data may be simultaneously written to the two or more memory block groups from among the plurality memory block groups, where i is a natural number less than M.

    摘要翻译： 提供了一种存储器单元编程方法和半导体器件，其可以能够同时将数据位和数据的另一位写入多个存储块。 其中将M位数据写入多个存储块的存储器编程方法可以包括数据分割操作和数据写入操作，其中M可以是自然数。 在数据划分操作中，多个存储块可以被划分为多个存储块组。 在数据写入操作中，数据的第i位可以从多个存储器块组中同时写入两个或更多个存储块组，然后数据的第i + 1位可以被同时写入两个或更多个 多个存储块组中的存储块组，其中i是小于M的自然数。

    Methods of operating nonvolatile memory devices
    4.
    发明授权
    Methods of operating nonvolatile memory devices 有权
    操作非易失性存储设备的方法

    公开(公告)号：US07791942B2

    公开(公告)日：2010-09-07

    申请号：US12073314

    申请日：2008-03-04

    申请人： Won-joo Kim ,  Tae-hee Lee ,  Jae-woong Hyun ,  Yoon-dong Park

    发明人： Won-joo Kim ,  Tae-hee Lee ,  Jae-woong Hyun ,  Yoon-dong Park

    IPC分类号： G11C16/04

    CPC分类号： G11C16/34

    摘要： Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell.

    摘要翻译： 提供了非易失性存储器件的操作方法。 在操作包括多个存储单元的非易失性存储器件的方法中，通过在其中记录有记录数据的存储单元的通道上感应升压电压来稳定记录数据。 从多个存储单元中选择存储单元，并且所选存储单元的通道上的升压电压由连接到所选存储单元的至少一个存储单元的通道电压引起。

    Method of writing/reading data into/from memory cell and page buffer using different codes for writing and reading operations
    5.
    发明授权
    Method of writing/reading data into/from memory cell and page buffer using different codes for writing and reading operations 有权
    使用不同的代码进行写入和读取操作，从存储单元和页面缓冲区写入/读取数据的方法

    公开(公告)号：US07729175B2

    公开(公告)日：2010-06-01

    申请号：US12010481

    申请日：2008-01-25

    申请人： Kyoung-lae Cho ,  Yoon-dong Park ,  Jun-jin Kong ,  Seung-hoon Lee ,  Jae-woong Hyun ,  Sung-jae Byun ,  Ju-hee Park ,  Seung-hwan Song

    发明人： Kyoung-lae Cho ,  Yoon-dong Park ,  Jun-jin Kong ,  Seung-hoon Lee ,  Jae-woong Hyun ,  Sung-jae Byun ,  Ju-hee Park ,  Seung-hwan Song

    IPC分类号： G11C11/34

    CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5642

    摘要： Provided are a method of writing/reading data into/from a memory cell and a page buffer using different codes for the writing and reading operations. The method of writing/reading data into/from a memory cell that has a plurality of threshold voltage distributions includes a data writing operation and a data reading operation. In the data writing operation, data having a plurality of bits is written into the memory cell by using a plurality of writing codes corresponding to threshold voltage distributions. In the data reading operation, the data having a plurality of bits is read from the memory cell by using reading codes corresponding to the threshold voltage distributions from among the threshold voltage distributions. In the method of writing/reading data into/from a memory cell, a part of the writing codes is different from a corresponding part of the reading codes.

    摘要翻译： 提供了一种将数据写入/从存储单元读取数据的方法和使用不同代码进行写入和读取操作的页面缓冲器。 对具有多个阈值电压分布的存储单元写入/读取数据的方法包括数据写入操作和数据读取操作。 在数据写入操作中，通过使用与阈值电压分布对应的多个写入代码，将具有多个位的数据写入存储单元。 在数据读取操作中，通过使用与阈值电压分布中的阈值电压分布相对应的读取代码，从存储单元读取具有多个位的数据。 在将数据写入/从存储单元读取的方法中，写入代码的一部分与读取代码的相应部分不同。

    Non-volatile memory device and method of manufacturing the same
    7.
    发明申请
    Non-volatile memory device and method of manufacturing the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US20100041224A1

    公开(公告)日：2010-02-18

    申请号：US12588064

    申请日：2009-10-02

    申请人： Yoon-Dong Park ,  Won-Joo Kim ,  June-Mo Koo ,  Suk-Pil Kim ,  Jae-Woong Hyun ,  Jung-Hoon Lee

    发明人： Yoon-Dong Park ,  Won-Joo Kim ,  June-Mo Koo ,  Suk-Pil Kim ,  Jae-Woong Hyun ,  Jung-Hoon Lee

    IPC分类号： H01L21/28

    CPC分类号： H01L27/115 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

    摘要： The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.

    摘要翻译： 非易失性存储器件可以包括具有主体和一对翅片的半导体衬底。 桥式绝缘层可以非电连接该对翅片的上部，以限定一对翅片之间的空隙。 一对翅片的外表面是一对翅片的不面向空隙的表面，并且一对翅片的内表面是面对空隙的一对翅片的表面。 非易失性存储器件还可以包括至少一个可覆盖该对散热片的外表面的至少一部分的控制栅极电极，可以在该桥绝缘层上延伸，并且可以与该半导体衬底隔离。 至少一对栅极绝缘层可以在至少一个控制栅极电极和一对散热片之间，并且至少一对存储节点可以位于至少一对栅极绝缘层之间，并且至少一个控制 栅电极。

    Fin-FET having GAA structure and methods of fabricating the same
    9.
    发明授权
    Fin-FET having GAA structure and methods of fabricating the same 有权
    具有GAA结构的Fin-FET及其制造方法

    公开(公告)号：US07514325B2

    公开(公告)日：2009-04-07

    申请号：US11505936

    申请日：2006-08-18

    申请人： Suk-Pil Kim ,  Jae-Woong Hyun ,  Yoon-Dong Park ,  Won-Joo Kim ,  Dong-Gun Park ,  Choong-Ho Lee

    发明人： Suk-Pil Kim ,  Jae-Woong Hyun ,  Yoon-Dong Park ,  Won-Joo Kim ,  Dong-Gun Park ,  Choong-Ho Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/42392 ,  H01L29/66795

    摘要： Example embodiments of the present invention relate to a semiconductor device and methods of fabricating the same. Other example embodiments of the present invention relate to a fin-field effect transistor (Fin-FET) having a fin-type channel region and methods of fabricating the same. A Fin-FET having a gate all around (GAA) structure that may use an entire area around a fin as a channel region is provided. The Fin-FET having the GAA structure includes a semiconductor substrate having a body, a pair of support pillars and a fin. The pair of support pillars may protrude from the body. A fin may be spaced apart from the body and may have ends connected to and supported by the pair of support pillars. A gate electrode may surround at least a portion of the fin of the semiconductor substrate. The gate electrode may be insulated from the semiconductor substrate. A gate insulation layer may be interposed between the gate electrode and the fin of the semiconductor substrate.

    摘要翻译： 本发明的示例性实施例涉及一种半导体器件及其制造方法。 本发明的其它示例性实施例涉及一种具有鳍型沟道区的鳍式场效应晶体管（Fin-FET）及其制造方法。 提供了可以使用围绕鳍片的整个区域作为沟道区域的具有栅极全（GAA）结构的鳍FET。 具有GAA结构的Fin-FET包括具有主体，一对支撑柱和鳍的半导体衬底。 一对支柱可能从身体突出。 翅片可以与主体间隔开，并且可以具有连接到一对支撑柱并由其支撑的端部。 栅电极可围绕半导体衬底的鳍的至少一部分。 栅电极可以与半导体衬底绝缘。 栅极绝缘层可以插入在半导体衬底的栅电极和鳍之间。