公开(公告)号：US20180276137A1

公开(公告)日：2018-09-27

申请号：US15465560

申请日：2017-03-21

申请人： ASHOK RAJ ,  SREENIVAS MANDAVA ,  SARATHY JAYAKUMAR ,  MOHAN J. KUMAR ,  THEODROS YIGZAW ,  RONALD N. STORY

发明人： ASHOK RAJ ,  SREENIVAS MANDAVA ,  SARATHY JAYAKUMAR ,  MOHAN J. KUMAR ,  THEODROS YIGZAW ,  RONALD N. STORY

IPC分类号： G06F12/1009 ,  G06F12/06 ,  G06F12/02 ,  G06F9/26

CPC分类号： G06F12/1009 ,  G06F9/268 ,  G06F9/3004 ,  G06F12/0215 ,  G06F12/0292 ,  G06F12/063 ,  G06F13/24 ,  G06F13/364 ,  G06F2212/65 ,  G06F2212/654

摘要： An apparatus and method are described for system physical address to memory module address translation. For example, one embodiment of an apparatus comprises: a fetch circuit of a core to fetch a system physical address (SPA) translate instruction from memory; a decode circuit of the core to decode the SPA translate instruction; a first register to store an SPA associated with the SPA translate instruction; a memory controller comprising one or more channel controllers to initiate a translation using the SPA, the memory controller to transmit a translation request to a first channel controller; the first channel controller to synthesize a response including dual in-line memory module (DIMM) address information; and a second register to store the DIMM address information to be used to identify the DIMM during subsequent memory transactions.

公开(公告)号：US20140281207A1

公开(公告)日：2014-09-18

申请号：US14133011

申请日：2013-12-18

申请人： Sreenivas Mandava ,  Brian S. Morris ,  Suneeta Sah ,  Roy M. Stevens ,  Ted Rossin ,  Mathew W. Stefaniw ,  John H. Crawford

发明人： Sreenivas Mandava ,  Brian S. Morris ,  Suneeta Sah ,  Roy M. Stevens ,  Ted Rossin ,  Mathew W. Stefaniw ,  John H. Crawford

IPC分类号： G11C11/406 ,  G11C14/00

CPC分类号： G11C14/0009 ,  G06F12/10 ,  G06F2212/1032 ,  G11C7/02 ,  G11C11/406

摘要： Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

摘要翻译： 公开了用于基于侵入者行的逻辑地址和与易失性存储器相关联的地址转换方案来确定易失性存储器的一个或多个受害行的逻辑地址的示例。 其他的例子被描述和要求保护。

公开(公告)号：US20140281206A1

公开(公告)日：2014-09-18

申请号：US14132987

申请日：2013-12-18

申请人： John H. Crawford ,  Brian S. Morris ,  Sreenivas Mandava ,  Raj K. Ramanujan

发明人： John H. Crawford ,  Brian S. Morris ,  Sreenivas Mandava ,  Raj K. Ramanujan

IPC分类号： G11C11/406

CPC分类号： G11C7/02 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  Y02D10/14

摘要： Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.

摘要翻译： 公开了用于概率动态随机存取存储器（DRAM）行修复的示例。 在一些示例中，使用DRAM的行敲击限制和DRAM的最大激活率可以确定概率行锤检测值。 然后可以使用概率行锤检测值，使得概率可接受地低，以致对DRAM的侵入行进行给定的激活导致在对一个或多个受害行进行相关联的执行调度的行刷新之前超过行敲击限制 与侵略者行。 其他的例子被描述和要求保护。