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    Double rounded combined floating-point multiply and add
    4.
    发明授权
    Double rounded combined floating-point multiply and add 有权
    双圆形组合浮点乘法和加法

    公开(公告)号：US09213523B2

    公开(公告)日：2015-12-15

    申请号：US13539198

    申请日：2012-06-29

    申请人： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

    发明人： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

    IPC分类号： G06F7/38 ,  G06F7/483 ,  G06F7/544

    CPC分类号： G06F7/4876 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/5443 ,  G06F2207/4802

    摘要： Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

    摘要翻译： 公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法，装置，指令和逻辑。 实施例包括检测浮点（FP）乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作，包括对FP乘法的结果进行舍入，随后是随后的FP操作。 所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行，所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测，第一和第二FP加法器来添加第三操作数加法尾数， 基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。 分别使用溢出检测选择最终结果。

    PARTIAL COMMITS IN DYNAMIC BINARY TRANSLATION BASED SYSTEMS
    6.
    发明申请
    PARTIAL COMMITS IN DYNAMIC BINARY TRANSLATION BASED SYSTEMS 有权
    基于动态二进制翻译的系统的部分组合

    公开(公告)号：US20150007153A1

    公开(公告)日：2015-01-01

    申请号：US13929360

    申请日：2013-06-27

    申请人： Raul Martinez ,  Enric Gibert Codina ,  Marc Lupon ,  Kyriakos A. Stavrou

    发明人： Raul Martinez ,  Enric Gibert Codina ,  Marc Lupon ,  Kyriakos A. Stavrou

    IPC分类号： G06F9/45 ,  G06F11/14

    CPC分类号： G06F8/443 ,  G06F8/4434

    摘要： Described herein are technologies for optimizing computer code. A code generator can optimize a portion of original code to create optimized code. The code generator can create a partial commit point to indicate that execution of the optimized code produces an invalid architectural state. The code generator can create recovery information recover a valid architectural state at a recovery point. The code generator can associate the partial commit point and recovery information with the optimized code.

    摘要翻译： 这里描述的是用于优化计算机代码的技术。 代码生成器可以优化原始代码的一部分以创建优化的代码。 代码生成器可以创建部分提交点，以指示优化代码的执行产生无效的架构状态。 代码生成器可以创建恢复信息，以在恢复点恢复有效的体系结构状态。 代码生成器可以将部分提交点和恢复信息与优化的代码相关联。

    RECONFIGURABLE PROCESSING UNIT
    10.
    发明申请
    RECONFIGURABLE PROCESSING UNIT 有权
    可重构加工单元

    公开(公告)号：US20150170021A1

    公开(公告)日：2015-06-18

    申请号：US14133192

    申请日：2013-12-18

    申请人： Marc Lupon ,  Enric Herrero Abellanas ,  Ayose Falcon ,  Fernando Latorre ,  Pedro Lopez ,  Frederico Pratas

    发明人： Marc Lupon ,  Enric Herrero Abellanas ,  Ayose Falcon ,  Fernando Latorre ,  Pedro Lopez ,  Frederico Pratas

    IPC分类号： G06N3/02

    CPC分类号： G06N3/063

    摘要： A processing device includes a processor core and a number of calculation modules that each is configurable to perform any one of operations for a convolutional neuron network system. A first set of the calculation modules are configured to perform convolution operations, a second set of the calculation modules are reconfigured to perform averaging operations, and a third set of the calculation modules are reconfigured to perform dot product operations.

    摘要翻译： 处理设备包括处理器核心和多个计算模块，每个计算模块可配置为执行卷积神经网络系统的任何一个操作。 第一组计算模块被配置为执行卷积运算，第二组计算模块被重新配置以执行平均运算，并且第三组计算模块被重新配置以执行点积运算。