公开(公告)号：US07480182B2

公开(公告)日：2009-01-20

申请号：US11486227

申请日：2006-07-13

申请人： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Lim

发明人： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Lim

IPC分类号： G11C6/06

CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： A program operation for a NOR flash memory device is verified by programming data in a memory cell, performing a dummy verify operation on the memory cell, and performing a program verify operation on the memory cell based on a result of the dummy verify operation.

摘要翻译： 通过在存储器单元中编程数据，对存储单元执行虚拟验证操作，并且基于虚拟验证操作的结果对存储器单元执行程序验证操作来验证NOR闪速存储器件的编程操作。

公开(公告)号：US07113418B2

公开(公告)日：2006-09-26

申请号：US10700389

申请日：2003-11-04

申请人： William L. Oberlin ,  Mark R. Simpson ,  Srinivas Venkataraman

发明人： William L. Oberlin ,  Mark R. Simpson ,  Srinivas Venkataraman

IPC分类号： G11C6/06 ,  G11C7/00

CPC分类号： H05K1/181 ,  G11C5/00 ,  H05K2201/09709 ,  H05K2201/10159 ,  H05K2201/10545 ,  Y02P70/611

摘要： Memory systems and methods are described. In one embodiment, a circuit board has front and back surfaces. At least one memory device having a plurality of pins is mounted on the front surface of the circuit board. At least one other memory device having a plurality of pins is mounted on the back surface of the circuit board. The memory devices are mounted on the circuit board such that at least some pins from the one memory device align with at least some pins of the other memory device to provide aligned pin pairs. A via is disposed in the circuit board and extends between and connects individual pins of an aligned pin pair.

摘要翻译： 描述了内存系统和方法。 在一个实施例中，电路板具有正面和背面。 具有多个引脚的至少一个存储器件安装在电路板的前表面上。 具有多个引脚的至少一个其它存储器件安装在电路板的后表面上。 存储器件安装在电路板上，使得来自一个存储器件的至少一些引脚与另一个存储器件的至少一些引脚对准以提供对准的引脚对。 通孔设置在电路板中，并且在对准的销对的各个销之间延伸并连接。

公开(公告)号：US07359228B2

公开(公告)日：2008-04-15

申请号：US11612144

申请日：2006-12-18

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C6/06

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

摘要翻译： 提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。 第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部 并且将第二块布置在其另一部分上。 存储单元阵列的端侧上的第一存储单元单元的结构与第二存​​储单元单元的结构不同。 用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

公开(公告)号：US07274582B2

公开(公告)日：2007-09-25

申请号：US11089541

申请日：2005-03-24

申请人： Dean A. Klein

发明人： Dean A. Klein

IPC分类号： G11C6/06 ,  G11C7/00

CPC分类号： G06F13/1684 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4234 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1072 ,  G11C11/4096

摘要： The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.

摘要翻译： 本发明包括数据处理系统及其组件。 这样的系统可以包括存储器控制器，多个存储器件，将存储器控制器与多个存储器件耦合的数据总线，以及位于存储器控制器和多个存储器之一之间的数据总线中的至少一个总线开关 设备。 还提供了包括数据总线中的至少一个开关的存储器集成电路和存储器模块。

公开(公告)号：US07242601B2

公开(公告)日：2007-07-10

申请号：US10853907

申请日：2004-05-25

申请人： André Dehon ,  Helia Naeimi

发明人： André Dehon ,  Helia Naeimi

IPC分类号： G11C6/06 ,  G11C7/00

CPC分类号： H03K19/1776 ,  B82Y10/00 ,  G11C5/063 ,  G11C8/10 ,  G11C11/34 ,  G11C11/54 ,  G11C29/025 ,  G11C29/08 ,  G11C29/76 ,  G11C29/816 ,  G11C29/832 ,  G11C2213/81 ,  H03K19/17736 ,  H03K19/17764 ,  H03K19/1778 ,  Y10S977/963

摘要： A method for constructing and addressing a nanoscale memory with known addresses and for tolerating defects which may arise during manufacture or device operational lifetime. During construction, nanoscale wires with addresses are stochastically assembled. During a programming phase, nanoscale wires are stochastically selected using their stochastic addresses through microscale inputs and a desired address code is associated with the selected nanoscale wires. Memory addresses are associated to the codes and then selected using the known codes during read/write operations from/to the memory.

摘要翻译： 一种用于构建和寻址具有已知地址的纳米尺度存储器并且用于容忍在制造或器件操作寿命期间可能出现的缺陷的方法。 在施工期间，地址的纳米级电线随机组装。 在编程阶段期间，使用其随机地址通过微量输入随机选择纳米线，并且所需的地址码与所选择的纳米尺度线相关联。 存储器地址与代码相关联，然后在从/到存储器的读/写操作期间使用已知代码进行选择。

公开(公告)号：US06870766B2

公开(公告)日：2005-03-22

申请号：US10300485

申请日：2002-11-19

申请人： Tae-Hee Cho ,  Yeong-Taek Lee

发明人： Tae-Hee Cho ,  Yeong-Taek Lee

IPC分类号： G11C8/08 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C6/06

CPC分类号： G11C7/04 ,  G11C8/08 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/3459

摘要： A multi-level semiconductor memory device preferably includes a plurality of wordlines connected to memory cells configured to store multi-level data. A first circuit supplies a temperature-responsive voltage to a selected wordline in order to read a state of a selected memory cell. A second circuit supplies a predetermined voltage to non-selected wordlines. The first circuit preferably includes a semiconductor element that varies its resistance in accordance with temperature. Reliable program-verifying and reading functions are preferably provided despite migration of threshold voltage distribution profiles due to temperature variations.

摘要翻译： 多级半导体存储器件优选地包括连接到被配置为存储多级数据的存储器单元的多条字线。 第一电路将温度响应电压提供给所选择的字线以便读取所选存储器单元的状态。 第二电路将预定电压提供给未选择的字线。 第一电路优选地包括根据温度改变其电阻的半导体元件。 尽管由于温度变化导致阈值电压分布曲线的迁移，但优选提供可靠的程序验证和读取功能。