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    CMOS COMPATIBLE LOW GATE CHARGE LATERAL MOSFET
    1.
    发明申请
    CMOS COMPATIBLE LOW GATE CHARGE LATERAL MOSFET 审中-公开
    CMOS兼容低栅极充电侧向MOSFET

    公开(公告)号：US20110115019A1

    公开(公告)日：2011-05-19

    申请号：US12618546

    申请日：2009-11-13

    Applicant: Frederick Perry Giles ,  Joel M. McGregor ,  Stephen McCormack

    Inventor： Frederick Perry Giles ,  Joel M. McGregor ,  Stephen McCormack

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7835 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7831

    Abstract: A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a switching gate positioned over a first portion of a channel region of the substrate, and a second portion forming a static gate formed over a second portion of the channel region and a transition region of the substrate. The static plate also extends over a drift region of the substrate, where the drift region is under a field oxide filled trench formed in the substrate. A switching voltage is applied to the switching gate and a constant voltage is applied to the static gate.

    Abstract translation: 分离栅功率晶体管包括横向配置的功率MOSFET，其包括掺杂硅衬底，形成在衬底的表面上的栅氧化层，以及形成在栅极氧化物层上的分裂多晶硅层。 多晶硅层被切割成两个电隔离部分，第一部分形成位于衬底的沟道区域的第一部分上方的开关栅极，以及形成在沟道区域的第二部分上形成的静态栅极的第二部分，以及 过渡区域。 静态板还在衬底的漂移区域上延伸，其中漂移区域位于形成在衬底中的场氧化物填充沟槽之下。 切换电压施加到开关栅极，并且恒定电压施加到静态栅极。

    PROTECTING MOBILE DEVICES USING DATA AND DEVICE CONTROL
    2.
    发明申请
    PROTECTING MOBILE DEVICES USING DATA AND DEVICE CONTROL 审中-公开
    使用数据和设备控制来保护移动设备

    公开(公告)号：US20110113242A1

    公开(公告)日：2011-05-12

    申请号：US12797367

    申请日：2010-06-09

    Applicant: Stephen McCormack

    Inventor： Stephen McCormack

    IPC: G06F12/14 ,  G06F17/30 ,  G06F1/00

    CPC classification number: G06F21/6218 ,  G06F2221/2147

    Abstract: A method for securing data on a mobile device includes establishing a remote connection between a server and a mobile device, receiving at the server a directory listing from the mobile device indicating files and folders stored on the mobile device, selecting one or more files or folders for securing on the mobile device, and transmitting from the server a secure command to the mobile device instructing the mobile device to secure the selected one or more files or folders. A system including a server and a mobile device can perform the method.

    Abstract translation: 一种用于在移动设备上保护数据的方法包括建立服务器与移动设备之间的远程连接，在服务器处接收来自移动设备的目录列表，指示存储在移动设备上的文件和文件夹，选择一个或多个文件或文件夹 用于固定在所述移动设备上，以及从所述服务器向所述移动设备发送安全命令，指示所述移动设备保护所选择的一个或多个文件或文件夹。 包括服务器和移动设备的系统可以执行该方法。

    Selective substrate implant process for decoupling analog and digital grounds
    6.
    发明授权
    Selective substrate implant process for decoupling analog and digital grounds 有权
    用于解耦模拟和数字接地的选择性衬底植入工艺

    公开(公告)号：US06395591B1

    公开(公告)日：2002-05-28

    申请号：US09733543

    申请日：2000-12-07

    Applicant: Stephen McCormack ,  Martin Alter ,  Robert S. Wrathall ,  Carlos Alberto Laber

    Inventor： Stephen McCormack ,  Martin Alter ,  Robert S. Wrathall ,  Carlos Alberto Laber

    IPC: H01L218238

    CPC classification number: H01L27/092 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892

    Abstract: An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for others P-wells not connected to any heavily doped regions and in which noise sensitive circuitry are built. The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for sensitive analog circuitry from the often noisy digital grounds of the digital and power switching circuitry.

    Abstract translation: 集成电路制造工艺包括选择性衬底注入工艺，以有效地将第一电源连接与第二电源连接分离，同时提供对寄生效应的抗扰性。 在一个实施例中，选择性衬底注入工艺仅在构建噪声产生电路的P阱下形成重掺杂的p型区域。 这些P阱的噪声接地连接与静态接地连接分离，对于未连接到任何重掺杂区域并且其中构建噪声敏感电路的其他P阱。 本发明的选择性衬底注入工艺在形成CMOS模拟集成电路方面具有特别的应用，其中重要的是使敏感模拟电路的模拟地与数字和功率开关电路的经常噪声的数字接地分离。

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