公开(公告)号：US09071246B2

公开(公告)日：2015-06-30

申请号：US11855740

申请日：2007-09-14

申请人： Suresh Subramaniam ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Jason Golbus ,  Dana L. How

发明人： Suresh Subramaniam ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Jason Golbus ,  Dana L. How

IPC分类号： G11C7/00 ,  H03K19/177 ,  G06F13/16

CPC分类号： G06F17/5054 ,  G06F13/1668 ,  G06F17/505 ,  G06F17/5077 ,  G11C7/00 ,  H03K19/177 ,  Y02D10/14

摘要： A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

摘要翻译： 一种包括可配置存储器控制器，存储器接口和可配置高速通信结构的系统，其包括布置在阵列中并可操作以实现多个流水线总线的多个互连站，其中可配置存储器控制器可操作地耦合到可配置 高速通信结构，其使用所述多个互连站中的第一互连站，其中所述存储器接口使用所述多个互连站中的第二互连站可操作地耦合到所述可配置高速通信结构，其中所述多个互连站被配置 以满足存储器接口的定时要求，并且其中可配置存储器控制器，存储器接口和可配置高速通信结构与可配置集成电路相关联。

公开(公告)号：US07557605B2

公开(公告)日：2009-07-07

申请号：US11855666

申请日：2007-09-14

申请人： Godfrey P. D'Souza ,  Douglas Laird ,  Malcolm J. Wing ,  Colin N. Murphy ,  Dana L. How ,  Robert Yu ,  Jay B. Patel ,  Ivo Dobbelaere ,  Jason Golbus ,  Suresh Subramaniam ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Dave Trossen ,  Kevin James

发明人： Godfrey P. D'Souza ,  Douglas Laird ,  Malcolm J. Wing ,  Colin N. Murphy ,  Dana L. How ,  Robert Yu ,  Jay B. Patel ,  Ivo Dobbelaere ,  Jason Golbus ,  Suresh Subramaniam ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Dave Trossen ,  Kevin James

IPC分类号： H03K19/173

CPC分类号： H03K19/177

摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.

摘要翻译： 一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速 网状互连结构被配置为实现横跨系统的多个互连管线总线。

公开(公告)号：US07494829B2

公开(公告)日：2009-02-24

申请号：US11864283

申请日：2007-09-28

申请人： Suresh Subramaniam ,  Amit Vijay Nahar ,  Thomas John Anderson ,  Kenneth Michael Butler ,  John Michael Carulli

发明人： Suresh Subramaniam ,  Amit Vijay Nahar ,  Thomas John Anderson ,  Kenneth Michael Butler ,  John Michael Carulli

IPC分类号： G01R31/26 ,  G06F17/18

CPC分类号： G01R31/2894

摘要： Systems and methods for identification of outlier semiconductor devices using data-driven statistical characterization are described herein. At least some preferred embodiments include a method that includes identifying a plurality of sample semiconductor chips that fail a production test as a result of subjecting the plurality of sample semiconductor chips to a stress inducing process, identifying at least one correlation between variations in a first sample parameter and variations in a second sample parameter (the sample parameters associated with the plurality of sample semiconductor chips) identifying as a statistical outlier chip any of a plurality of production semiconductor chips that pass the production test and that further do not conform to a parameter constraint generated based upon the at least one correlation identified and upon data associated with at least some of the plurality of production semiconductor chips, and segregating the statistical outlier chip from the plurality of production semiconductor chip.

摘要翻译： 本文描述了使用数据驱动的统计表征来识别离群半导体器件的系统和方法。 至少一些优选实施例包括一种方法，其包括：通过对所述多个样品半导体芯片进行应力诱导过程，识别出第一样品中的变化之间的至少一个相关性，从而识别不能进行生产测试的多个样品半导体芯片 第二样本参数（与多个样本半导体芯片相关联的样本参数）的参数和变化，其识别通过生产测试的多个生产半导体芯片中的任一个的统计离群芯片，并且进一步不符合参数约束 基于所识别的所述至少一个相关性和与所述多个生产半导体芯片中的至少一些生成半导体芯片相关联的数据生成，并且将所述统计离群值芯片与所述多个生产半导体芯片分离。

公开(公告)号：US20080262793A1

公开(公告)日：2008-10-23

申请号：US11864283

申请日：2007-09-28

申请人： Suresh SUBRAMANIAM ,  Amit Vijay NAHAR ,  Thomas John ANDERSON ,  Kenneth Michael BUTLER ,  John Michael CARULLI

发明人： Suresh SUBRAMANIAM ,  Amit Vijay NAHAR ,  Thomas John ANDERSON ,  Kenneth Michael BUTLER ,  John Michael CARULLI

IPC分类号： G06F17/18

CPC分类号： G01R31/2894

摘要： Systems and methods for identification of outlier semiconductor devices using data-driven statistical characterization are described herein. At least some preferred embodiments include a method that includes identifying a plurality of sample semiconductor chips that fail a production test as a result of subjecting the plurality of sample semiconductor chips to a stress inducing process, identifying at least one correlation between variations in a first sample parameter and variations in a second sample parameter (the sample parameters associated with the plurality of sample semiconductor chips) identifying as a statistical outlier chip any of a plurality of production semiconductor chips that pass the production test and that further do not conform to a parameter constraint generated based upon the at least one correlation identified and upon data associated with at least some of the plurality of production semiconductor chips, and segregating the statistical outlier chip from the plurality of production semiconductor chip.

摘要翻译： 本文描述了使用数据驱动的统计表征来识别离群半导体器件的系统和方法。 至少一些优选实施例包括一种方法，其包括：通过对所述多个样品半导体芯片进行应力诱导过程，识别出第一样品中的变化之间的至少一个相关性，从而识别不能进行生产测试的多个样品半导体芯片 第二样本参数（与多个样本半导体芯片相关联的样本参数）的参数和变化，其识别通过生产测试的多个生产半导体芯片中的任一个的统计离群芯片，并且进一步不符合参数约束 基于所识别的所述至少一个相关性和与所述多个生产半导体芯片中的至少一些生成半导体芯片相关联的数据生成，并且将所述统计离群值芯片与所述多个生产半导体芯片分离。

公开(公告)号：US07129735B2

公开(公告)日：2006-10-31

申请号：US10938488

申请日：2004-09-10

申请人： Suresh Subramaniam ,  Kenneth M. Butler ,  John M. Carulli ,  Richard A. Lawrence

发明人： Suresh Subramaniam ,  Kenneth M. Butler ,  John M. Carulli ,  Richard A. Lawrence

IPC分类号： G01R31/26

CPC分类号： G01R31/2894 ,  G01R31/287

摘要： A method for test data-driven detection of outlier semiconductor devices. Some illustrative embodiments may be a method used to test a semiconductor die comprising performing a burn-in test of a plurality of sample semiconductor dies to identify a failure of a defective semiconductor die, correlating variations in a parameter with the failure (the parameter comprising a characteristic associated with the plurality of sample semiconductor dies), defining a parameter constraint associated with the parameter, performing a production test of a production semiconductor die, and identifying the production semiconductor die as an outlier semiconductor die (the outlier semiconductor die passing the production test, but failing to conform to the parameter constraint).

摘要翻译： 一种用于离群半导体器件的测试数据驱动检测的方法。 一些示例性实施例可以是用于测试半导体管芯的方法，包括执行多个样品半导体管芯的老化测试以识别缺陷半导体管芯的故障，使参数的变化与故障相关联（参数包括 特征与多个样品半导体管芯相关联），限定与该参数相关的参数约束，执行生产半导体管芯的生产测试，以及将生产半导体管芯识别为离群半导体管芯（通过生产测试的离群半导体管芯 ，但不符合参数约束）。

公开(公告)号：US20090072858A1

公开(公告)日：2009-03-19

申请号：US11855666

申请日：2007-09-14

申请人： Godfrey P. D'Souza ,  Douglas Laird ,  Malcolm J. Wing ,  Colin N. Murphy ,  Dana L. How ,  Robert Yu ,  Jay B. Patel ,  Ivo Dobbelaere ,  Jason Golbus ,  Suresh Subramaniam ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Dave Trossen ,  Kevin James

发明人： Godfrey P. D'Souza ,  Douglas Laird ,  Malcolm J. Wing ,  Colin N. Murphy ,  Dana L. How ,  Robert Yu ,  Jay B. Patel ,  Ivo Dobbelaere ,  Jason Golbus ,  Suresh Subramaniam ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Dave Trossen ,  Kevin James

IPC分类号： H03K19/173

CPC分类号： H03K19/177

摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.

摘要翻译： 一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速 网状互连结构被配置为实现横跨系统的多个互连管线总线。

公开(公告)号：US08126681B2

公开(公告)日：2012-02-28

申请号：US12566387

申请日：2009-09-24

申请人： Amit V Nahar ,  John M Carulli ,  Kenneth M Butler ,  Thomas J Anderson ,  Suresh Subramaniam

发明人： Amit V Nahar ,  John M Carulli ,  Kenneth M Butler ,  Thomas J Anderson ,  Suresh Subramaniam

IPC分类号： G06F19/00

CPC分类号： G01R31/31718

摘要： A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain electrical test data including at least one test parameter, applying at least a first data transform processing methodology to the electrical test data to generate processed test data, and applying a second data transform processing methodology that is different from the first data transform processing methodology to process the processed test data. The second data transform processing methodology applies an outlier test limit to identify non-outlier devices that comprise semiconductor devices from the semiconductor devices that conform to the outlier test limit and outlier devices that do not conform to the outlier test limit. The semiconductor devices are dispositioned using the outlier identification results. At least one of the data transform processing methodologies can include statistics.

摘要翻译： 一种用于从多个半导体器件识别离群半导体器件的方法包括执行至少一个电测试以获得包括至少一个测试参数的电测试数据，对电测试数据应用至少第一数据变换处理方法以产生经处理的测试 数据，以及应用与第一数据变换处理方法不同的第二数据变换处理方法来处理处理的测试数据。 第二数据变换处理方法应用异常值测试极限以识别来自符合离群值测试极限的半导体器件的半导体器件的非离子化器件以及不符合离群值测试极限的异常值器件。 使用异常值识别结果对半导体器件进行配置。 数据变换处理方法中的至少一个可以包括统计。

公开(公告)号：US20090072856A1

公开(公告)日：2009-03-19

申请号：US11855740

申请日：2007-09-14

申请人： Suresh Subramaniam ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Jason Golbus ,  Dana L. How

发明人： Suresh Subramaniam ,  Mukunda Krishnappa ,  Pohrong R. Chu ,  Jason Golbus ,  Dana L. How

IPC分类号： H03K19/173

CPC分类号： G06F17/5054 ,  G06F13/1668 ,  G06F17/505 ,  G06F17/5077 ,  G11C7/00 ,  H03K19/177 ,  Y02D10/14

摘要： A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

摘要翻译： 一种包括可配置存储器控制器，存储器接口和可配置高速通信结构的系统，其包括布置在阵列中并且可操作以实现多个流水线总线的多个互连站，其中可配置存储器控制器可操作地耦合到可配置 高速通信结构，其使用所述多个互连站中的第一互连站，其中所述存储器接口使用所述多个互连站中的第二互连站可操作地耦合到所述可配置高速通信结构，其中所述多个互连站被配置 以满足存储器接口的定时要求，并且其中可配置存储器控制器，存储器接口和可配置高速通信结构与可配置集成电路相关联。

公开(公告)号：US20060028229A1

公开(公告)日：2006-02-09

申请号：US10938488

申请日：2004-09-10

申请人： Suresh Subramaniam ,  Kenneth Butler ,  John Carulli ,  Richard Lawrence

发明人： Suresh Subramaniam ,  Kenneth Butler ,  John Carulli ,  Richard Lawrence

IPC分类号： G01R31/26

CPC分类号： G01R31/2894 ,  G01R31/287

摘要： A method for test data-driven detection of outlier semiconductor devices. Some illustrative embodiments may be a method used to test a semiconductor die comprising performing a burn-in test of a plurality of sample semiconductor dies to identify a failure of a defective semiconductor die, correlating variations in a parameter with the failure (the parameter comprising a characteristic associated with the plurality of sample semiconductor dies), defining a parameter constraint associated with the parameter, performing a production test of a production semiconductor die, and identifying the production semiconductor die as an outlier semiconductor die (the outlier semiconductor die passing the production test, but failing to conform to the parameter constraint).

公开(公告)号：US20110071782A1

公开(公告)日：2011-03-24

申请号：US12566387

申请日：2009-09-24

申请人： AMIT V. NAHAR ,  JOHN M. CARULLI, JR. ,  KENNETH M. BUTLER ,  THOMAS J. ANDERSON ,  SURESH SUBRAMANIAM

发明人： AMIT V. NAHAR ,  JOHN M. CARULLI, JR. ,  KENNETH M. BUTLER ,  THOMAS J. ANDERSON ,  SURESH SUBRAMANIAM

IPC分类号： G06F19/00 ,  G01N37/00 ,  G06F17/18

CPC分类号： G01R31/31718

摘要： A method for identifying outlier semiconductor devices from a plurality of semiconductor devices includes performing at least one electrical test to obtain electrical test data including at least one test parameter, applying at least a first data transform processing methodology to the electrical test data to generate processed test data, and applying a second data transform processing methodology that is different from the first data transform processing methodology to process the processed test data. The second data transform processing methodology applies an outlier test limit to identify non-outlier devices that comprise semiconductor devices from the semiconductor devices that conform to the outlier test limit and outlier devices that do not conform to the outlier test limit. The semiconductor devices are dispositioned using the outlier identification results. At least one of the data transform processing methodologies can include statistics.

摘要翻译： 一种用于从多个半导体器件识别离群半导体器件的方法包括执行至少一个电测试以获得包括至少一个测试参数的电测试数据，对电测试数据应用至少第一数据变换处理方法以产生经处理的测试 数据，以及应用与第一数据变换处理方法不同的第二数据变换处理方法来处理处理的测试数据。 第二数据变换处理方法应用异常值测试极限以识别来自符合离群值测试极限的半导体器件的半导体器件的非离子化器件以及不符合离群值测试极限的异常值器件。 使用异常值识别结果对半导体器件进行配置。 数据变换处理方法中的至少一个可以包括统计。