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20 条记录 (耗时 0.014 秒)

    Method of fabricating semiconductor light-emitting devices with isolation trenches
    2.
    发明授权
    Method of fabricating semiconductor light-emitting devices with isolation trenches 失效
    制造具有隔离沟槽的半导体发光器件的方法

    公开(公告)号：US07754512B2

    公开(公告)日：2010-07-13

    申请号：US11119805

    申请日：2005-05-03

    申请人： Masumi Taninaka ,  Hiroyuki Fujiwara ,  Susumu Ozawa ,  Masaharu Nobori

    发明人： Masumi Taninaka ,  Hiroyuki Fujiwara ,  Susumu Ozawa ,  Masaharu Nobori

    IPC分类号： H01L33/00 ,  H01L21/00 ,  H01L33/08

    CPC分类号： B41J2/45 ,  H01L27/153

    摘要： According to the present invention, a light-emitting semiconductor device has light-emitting elements separated by isolation trenches, preferably on two sides of each light-emitting element. The device may be fabricated by forming a single band-shaped diffusion region, then forming trenches that divide the diffusion region into multiple regions, or by forming individual diffusion regions and then forming trenches between them. The trenches prevent overlap between adjacent light-emitting elements, regardless of their junction depth, enabling a high-density array to be fabricated while maintaining adequate junction depth.

    摘要翻译： 根据本发明，发光半导体器件具有通过隔离沟槽分离的发光元件，优选在每个发光元件的两侧。 该器件可以通过形成单个带状扩散区域，然后形成将扩散区域分成多个区域的沟槽，或者通过形成各个扩散区域，然后在它们之间形成沟槽来制造。 沟槽防止相邻发光元件之间的重叠，而不管它们的结深度如何，使得能够制造高密度阵列同时保持足够的结深度。

    Semiconductor array device with single interconnection layer
    4.
    发明授权
    Semiconductor array device with single interconnection layer 有权

    公开(公告)号：US06781246B2

    公开(公告)日：2004-08-24

    申请号：US10631893

    申请日：2003-08-01

    申请人： Hiroyuki Fujiwara ,  Masumi Taninaka ,  Susumu Ozawa ,  Masumi Koizumi

    发明人： Hiroyuki Fujiwara ,  Masumi Taninaka ,  Susumu Ozawa ,  Masumi Koizumi

    IPC分类号： H01L2348

    CPC分类号： B41J2/45 ,  H01L27/153 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An array of semiconductor circuit elements such as light-emitting elements includes a semiconductor layer partially covered by a dielectric film. A first interconnecting pad such as a wire-bonding pad is electrically coupled by conductive paths passing through the semiconductor layer to electrodes of a first group of semiconductor circuit elements formed in the semiconductor layer. A second interconnecting pad such as a wire-bonding pad, formed on the dielectric film, is electrically coupled to electrodes of a second group of semiconductor circuit elements formed in the semiconductor layer by conductive paths insulated from the semiconductor layer by the dielectric film. The second conductive paths cross the first conductive paths at points at which the first conductive paths pass through the semiconductor layer, so that only a single layer of metal interconnecting lines is needed.

    Bulk loaded coin dispensing machine
    6.
    发明授权
    Bulk loaded coin dispensing machine 失效
    散装硬币分发机

    公开(公告)号：US4840290A

    公开(公告)日：1989-06-20

    申请号：US19547

    申请日：1987-02-26

    申请人： Shunichi Nakamura ,  Kouichi Iimura ,  Kikuo Nakamura ,  Susumu Ozawa

    发明人： Shunichi Nakamura ,  Kouichi Iimura ,  Kikuo Nakamura ,  Susumu Ozawa

    IPC分类号： G07D1/04 ,  G07D9/00

    CPC分类号： G07D1/04 ,  G07D9/00

    摘要： A coin exchanging machine has a coin case disposed at the bottom of a casing for accommodating a plurality of coin bundles, a coin pushing mechanism for pushing laterally a row of coin bundles piled up in the coin case, and a coin transferring mechanism for receiving a row of coin bundles from the coin case by pushing the coin bundles by the coin pushing mechanism and for feeding the coin bundles one by one into a coin accommodating space in response to the discharge of the coin bundles.

    摘要翻译： 硬币交换机具有设置在用于容纳多个硬币包的壳体的底部的硬币盒，用于向侧面推出堆叠在硬币盒中的一排硬币包的硬币推送机构，以及用于接收 通过由硬币推动机构推动硬币包，并将硬币包一个一个地投入到硬币容纳空间中以响应于硬币包的排出而从硬币盒中排出硬币束。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08755211B2

    公开(公告)日：2014-06-17

    申请号：US13401113

    申请日：2012-02-21

    申请人： Susumu Ozawa

    发明人： Susumu Ozawa

    IPC分类号： G11C5/02

    CPC分类号： G11C5/025 ,  G11C7/18 ,  G11C16/0483 ,  G11C16/20 ,  H01L27/11582

    摘要： According to one embodiment, a semiconductor memory device comprises a first silicon pillar including a first pair of columnar portions and a first connection portion, a second silicon pillar including a second pair of columnar portions and a second connection portion in the shunt region, the second silicon pillar being adjacent to the first silicon pillar, a first interconnection connected to one of the first pair of columnar portions of the first silicon pillar, a second interconnection connected to one of the second pair of columnar portions of the second silicon pillar. The first interconnection is connected to a dummy bit line. The first interconnection and the second interconnection are connected on the same level.

    摘要翻译： 根据一个实施例，一种半导体存储器件包括：第一硅柱，其包括第一对柱状部分和第一连接部分;第二硅柱柱，包括第二对柱状部分;以及第二连接部分， 硅柱与第一硅柱相邻，第一互连连接到第一硅柱的第一对柱状部分之一，第二互连件连接到第二硅柱的第二对柱状部分之一。 第一互连连接到虚拟位线。 第一互连和第二互连连接在同一级。