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公开(公告)号：US06469966B1
公开(公告)日：2002-10-22
申请号：US09360329
申请日：1999-07-23
IPC分类号： G11B700
CPC分类号： G11B19/128 , G11B7/0903
摘要： In a disc apparatus, a tracking error signal from an optical pickup is outputted to a micro-computer. The micro-computer discriminates a disc that is different in bit density (track pitch) based on amplitude and/or waveform of the tracking error signal.
摘要翻译： 在光盘装置中，来自光学拾取器的跟踪误差信号被输出到微型计算机。 微计算机基于跟踪误差信号的幅度和/或波形来鉴别位密度（轨道间距）不同的盘。
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2.发明授权Semiconductor memory device having a back gate voltage controlled delay circuit 有权具有背栅电压控制延迟电路的半导体存储器件
公开(公告)号：US6034920A
公开(公告)日：2000-03-07
申请号：US198816
申请日：1998-11-24
摘要： A semiconductor memory device has an address buffer (200, 230). A pre-decoder circuit (202, 232) receives the output of the address buffer (200, 230), and a memory array (212) receives the output of the pre-decoder circuit. A main amplifier (216, 248) in turn receives the output of the memory array (212, 244). An address transition detector (ATD) pulse generator circuit (204, 234) also receives the output of the address buffer (200, 230), and a pulse delay circuit (208, 240) receives the output of the address transition detector pulse generator circuit (204, 234). The pulse delay circuit (208, 240) also provides a main amplifier signal to the main amplifier (216, 248). The memory device further includes a voltage generator (206, 236) that generates a back gate voltage which is provided as a low voltage supply (V.sub.BB) for the address transition detector (ATD) pulse generator circuit (204, 234) and the pulse delay circuit (208, 240). The address transition detector (ATD) pulse generator (204, 234) and the pulse delay circuit (208, 240) have a delay that is controlled by the back gate voltage (V.sub.BB) and has a reduced dependency on a high voltage supply (V.sub.DD) of the memory device.
摘要翻译： 半导体存储器件具有地址缓冲器（200,230）。 预解码器电路（202,232）接收地址缓冲器（200,230）的输出，存储器阵列（212）接收预解码器电路的输出。 主放大器（216,248）又接收存储器阵列（212,244）的输出。 地址转换检测器（ATD）脉冲发生器电路（204,234）还接收地址缓冲器（200,230）的输出，并且脉冲延迟电路（208,240）接收地址转换检测器脉冲发生器电路的输出 （204,234）。 脉冲延迟电路（208,240）还向主放大器（216,248）提供主放大器信号。 存储装置还包括产生背栅电压的电压发生器（206,236），该栅极电压作为用于地址转换检测器（ATD）脉冲发生器电路（204,234）的低电压电源（VBB）和脉冲延迟 电路（208,240）。 地址转换检测器（ATD）脉冲发生器（204,234）和脉冲延迟电路（208,240）具有由背栅极电压（VBB）控制的延迟，并且对高电压源（VDD）的依赖性降低 ）的存储器件。
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公开(公告)号：US5768214A
公开(公告)日：1998-06-16
申请号：US689548
申请日：1996-08-09
IPC分类号： G11C11/41 , G11C7/06 , G11C8/18 , G11C11/409 , G11C8/00
摘要： A semiconductor memory device in which erroneous operation with respect to undesired level changes of the input address signal is prevented, and appropriate operation of the main amplifier is ensured. The semiconductor memory device has a main amplifier activating pulse generator 112' which includes response sensitivity reduction circuit 10, response sensitivity selector 12, and main amplifier activating pulse generator 14. The response sensitivity reduction circuit 10 can reduce the response sensitivity or input sensitivity of the circuit 112' with respect to an input address transition detection pulse ATD. The response sensitivity selector 12 selects either a first input terminal A1 or a second input terminal A2, depending on the output state of the main amplifier activating pulse generator 14. Consequently, when there is no output of a main amplifier activating pulse MA from the main amplifier activating pulse generator 14, the response sensitivity selector 12 switches to first input terminal A1 to select response sensitivity reduction circuit 10; when a main amplifier activating pulse MA is output, the selector 12 switches to second input terminal A2 to select bypass circuit 11.
摘要翻译： 一种半导体存储器件，其中防止了与输入地址信号的不期望的电平变化有关的错误操作，并且确保了主放大器的适当的操作。 半导体存储器件具有主放大器激活脉冲发生器112'，其包括响应灵敏度降低电路10，响应灵敏度选择器12和主放大器激活脉冲发生器14.响应灵敏度降低电路10可以降低响应灵敏度降低电路10的响应灵敏度或输入灵敏度 电路112'相对于输入地址转换检测脉冲ATD。 响应灵敏度选择器12根据主放大器激活脉冲发生器14的输出状态选择第一输入端子A1或第二输入端子A2。因此，当没有主放大器从主振荡器激活脉冲MA的输出 放大器激活脉冲发生器14，响应灵敏度选择器12切换到第一输入端子A1以选择响应灵敏度降低电路10; 当输出主放大器激活脉冲MA时，选择器12切换到第二输入端A2以选择旁路电路11。
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公开(公告)号：US4890262A
公开(公告)日：1989-12-26
申请号：US142969
申请日：1988-01-12
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G11C29/44
CPC分类号： G11C29/76
摘要： A semiconductor memory device which has a memory portion and a counter to count rows and/or columns of the memory portion, the counter being so constructed to return to a reset mode at the beginning of an address counting sequence when coming up to an arbitrary address such that an address or addresses corresponding to a region of the memory containing one or more defective memory cells and occurring after the arbitrary address are inaccessible. The counter thereby comprises a defective bit relief circuit built into the memory device.
摘要翻译： 一种半导体存储器件，其具有存储部分和计数器以对存储器部分的行和/或列进行计数，该计数器被构造为当到达任意地址时在地址计数序列开始时返回到复位模式 使得对应于包含一个或多个缺陷存储器单元并且在任意地址之后发生的存储器的区域的地址或地址是不可访问的。 因此，该计数器包括内置于存储装置中的有缺陷的位释放电路。
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公开(公告)号：US6088314A
公开(公告)日：2000-07-11
申请号：US009076
申请日：1998-01-20
IPC分类号： G11B7/0037 , G11B19/12 , G11B20/10 , G11B5/09 , G11B15/46
CPC分类号： G11B19/12 , G11B20/10 , G11B7/0037
摘要： A disc reading apparatus includes a microcomputer. The microcomputer calculates, based on amount data, an outer radius (RM) of an area that is recording data. The reading speed on the determined outer radius is set to a previously set speed (V.sub.2) for the outer circumference. When reading desired data, a radius of an inner circumference (r) of the data-recorded area is calculated from time information (identification data) to calculate a reading speed (V.sub.n) for reading the data. That is, since the disc contains data recorded such that the linear velocity per unit area becomes constant, the position of a pick-up and the reading speed are represented by a generally inversely proportional linear equation. Therefore, the reading speed (V.sub.n) can be calculated based on the inner radius (r) of the area recording the data to be read, the inner and outer radii (RS, RM) of the data-recorded area, and previously set inner and outer speeds (V.sub.1, V.sub.2).
摘要翻译： 盘读取装置包括微型计算机。 微计算机根据量数据计算正在记录数据的区域的外半径（RM）。 将确定的外半径上的读取速度设定为对于外周的预先设定的速度（V2）。 当读取所需数据时，根据时间信息（识别数据）计算数据记录区域的内圆周（r）的半径，以计算用于读取数据的读取速度（Vn）。 也就是说，由于盘包含记录的数据，使得每单位面积的线速度变得恒定，拾取的位置和读取速度由大致成反比的线性方程表示。 因此，读取速度（Vn）可以基于记录要读取的数据的区域的内半径（r），数据记录区域的内半径（RS，RM）和预先设定的内部 和外部速度（V1，V2）。
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公开(公告)号：US4653030A
公开(公告)日：1987-03-24
申请号：US646655
申请日：1984-08-31
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A semiconductor dynamic read/write memory of the multiplexed-address type employs an on-chip refresh counter which is activated by CAS-before-RAS sequence. This counter is made up of stages almost identical to the row address buffers so the same clocks can be used. Either the address input buffers or the refresh counter stages are gated into second-stage row address buffers, and carry feedback from these second stage buffers to the counter stages is used to increment the counter. The access time of the memory for normal read or write is not degraded by the refresh circuitry.
摘要翻译： 复用地址类型的半导体动态读/写存储器采用片上刷新计数器，该计数器由＆upbar＆C-before-＆upbar＆R序列激活。 该计数器由与行地址缓冲器几乎相同的级组成，因此可以使用相同的时钟。 地址输入缓冲器或刷新计数器级被选通到第二级行地址缓冲器中，并且从这些第二级缓冲器到计数器级的进位反馈被用于递增计数器。 正常读或写存储器的访问时间不会被刷新电路降级。
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公开(公告)号：US5841688A
公开(公告)日：1998-11-24
申请号：US883738
申请日：1997-06-27
IPC分类号： G11C5/06 , G11C8/14 , G11C11/408 , H01L21/8242 , H01L27/108 , G11C5/00
CPC分类号： H01L27/10891 , G11C11/408 , G11C5/063 , G11C8/14 , H01L27/10897
摘要： A circuit is designed with a first lower conductor (500) having two ends. One end of the first lower conductor is coupled to a first signal source (386). A first upper conductor (544) has two ends and is spaced apart from the first lower conductor by a distance less than an allowable spacing between adjacent lower conductors. One end of the first upper conductor is coupled to a second signal source (384). A second upper conductor (508) has two ends. One end of the second upper conductor is coupled to another end of the first lower conductor for receiving a signal from the first signal source. A second lower conductor (552) has two ends and is spaced apart from the second upper conductor by a distance less than the allowable spacing between adjacent lower conductors. One end of the second lower conductor is coupled to another end of the first upper conductor for receiving a signal from the second signal source. Since the upper and lower conductors are spaced apart by a distance less than an allowable spacing between adjacent lower conductors, layout area is conserved. Total resistance of conductors connected to each signal source is the same, so signal delay is the same.
摘要翻译： 电路设计有具有两端的第一下导体（500）。 第一下导体的一端耦合到第一信号源（386）。 第一上导体（544）具有两个端部，并且与第一下导体间隔一个小于相邻下导体之间允许间隔的距离。 第一上导体的一端耦合到第二信号源（384）。 第二上导体（508）具有两端。 第二上导体的一端耦合到第一下导体的另一端，用于接收来自第一信号源的信号。 第二下导体（552）具有两个端部，并且与第二上导体间隔一个小于相邻下导体之间允许间隔的距离。 第二下导体的一端耦合到第一上导体的另一端，用于从第二信号源接收信号。 由于上导体和下导体间隔距离小于相邻下导体之间的允许间距，所以布局面积是保守的。 连接到每个信号源的导体的总电阻是相同的，因此信号延迟是相同的。
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公开(公告)号：US4862413A
公开(公告)日：1989-08-29
申请号：US180648
申请日：1988-04-04
摘要： A memory device including a voltage stepdown circuit is proposed in which a reduced reference voltage is produced from a supplied reference voltage and is passed to the selected one of the row lines of the memory array after all the row lines are discharged to ground potential, while the supplied reference voltage is fed directly, viz., without reduction, to all the control circuits of the device. The voltage stepdown circuit provided in the memory device is thus relieved from the burden to supply current to the control circuits and has only to feed the selected one of the row lines so that the field-effect transistors forming the voltage stepdown circuit can be fabricated to have channel regions with significantly reduced widths.
摘要翻译： 提出了包括降压电路的存储器件，其中从所提供的参考电压产生降低的参考电压，并且在所有行线被放电到地电位之后被传递到存储器阵列的选定行之一行，同时 所提供的参考电压直接馈送到设备的所有控制电路，即不减少。 因此，设置在存储装置中的降压电路免除了向控制电路提供电流的负担，并且仅供给所选择的一行行线，使得形成降压电路的场效应晶体管可以制造成 具有显着减小宽度的通道区域。
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9.发明授权Optical disk device capable of preventing collision between disk and objective lens, and control method thereof 失效能够防止盘与物镜之间的碰撞的光盘装置及其控制方法公开(公告)号：US07397735B2
公开(公告)日：2008-07-08
申请号：US10859786
申请日：2004-06-03
申请人： Tadashi Tachibana
发明人： Tadashi Tachibana
IPC分类号： G11B7/09
CPC分类号： G11B7/0946 , G11B7/121 , G11B11/1055
摘要： The magnitude (Ga) of an impact applied to a lens holder is constantly monitored based on an output of an impact sensor. When it is determined that Ga exceeds Gth, focus servo is released, and the lens holder is provided with a force to make it move away from a disk. Upon recheck of Ga, when it is determined that Ga is now equal to or less than Gth, the force having been provided to the lens holder is cancelled, and the focus servo is resumed.
摘要翻译： 基于冲击传感器的输出来不断地监视施加到透镜架的冲击的大小（Ga）。 当确定Ga超过Gth时，聚焦伺服被释放，并且镜头保持器被设置成使其远离盘移动的力。 在重新检查Ga时，当确定Ga现在等于或小于Gth时，已经提供给透镜架的力被消除，并且聚焦伺服被恢复。
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公开(公告)号：US07012872B2
公开(公告)日：2006-03-14
申请号：US09752726
申请日：2001-01-03
IPC分类号： G11B5/09
CPC分类号： G11B20/10527 , G11B7/005 , G11B7/00736 , G11B20/225 , G11B2007/0013
摘要： When an optical disc is set to the motor, the slice level is set to a slice level Sk as a reference slice level and a measured jitter value A (S0, S1) is produced. The slice level is incremented in steps of a fixed quantity Si (S2). Then, a measured jitter value B obtained at the incremented slice level is compared with the previous measured jitter value A (S3, S4). This sequence of process is repeated, and when the measured jitter value A is smaller than the counter value, it is judged that the jitter changes its quantity varying direction to a decreasing direction. Then, the incrementing operation of the slice level is immediately stopped, and the slice level is decremented in steps of another fixed quantity Sd (
摘要翻译： 当将光盘设置到电动机时，将限幅电平设置为限幅电平Sk作为参考限幅电平，并且产生测量的抖动值A（S 0，S 1）。 限幅电平以固定量Si（S 2）的步长递增。 然后，将在增加的限幅电平处获得的测量抖动值B与先前测量的抖动值A进行比较（S 3，S 4）。 重复该处理顺序，并且当测量的抖动值A小于计数器值时，判断抖动将其数量变化方向改变为减小的方向。 然后，切片电平的递增操作立即停止，并且限幅电平以另一固定量Sd（
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