公开(公告)号：US5768214A

公开(公告)日：1998-06-16

申请号：US689548

申请日：1996-08-09

申请人： Ken Saitoh ,  Shunichi Sukegawa ,  Tadashi Tachibana ,  Makoto Saeki ,  Yukihide Suzuki

发明人： Ken Saitoh ,  Shunichi Sukegawa ,  Tadashi Tachibana ,  Makoto Saeki ,  Yukihide Suzuki

IPC分类号： G11C11/41 ,  G11C7/06 ,  G11C8/18 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C8/18 ,  G11C7/06

摘要： A semiconductor memory device in which erroneous operation with respect to undesired level changes of the input address signal is prevented, and appropriate operation of the main amplifier is ensured. The semiconductor memory device has a main amplifier activating pulse generator 112' which includes response sensitivity reduction circuit 10, response sensitivity selector 12, and main amplifier activating pulse generator 14. The response sensitivity reduction circuit 10 can reduce the response sensitivity or input sensitivity of the circuit 112' with respect to an input address transition detection pulse ATD. The response sensitivity selector 12 selects either a first input terminal A1 or a second input terminal A2, depending on the output state of the main amplifier activating pulse generator 14. Consequently, when there is no output of a main amplifier activating pulse MA from the main amplifier activating pulse generator 14, the response sensitivity selector 12 switches to first input terminal A1 to select response sensitivity reduction circuit 10; when a main amplifier activating pulse MA is output, the selector 12 switches to second input terminal A2 to select bypass circuit 11.

摘要翻译： 一种半导体存储器件，其中防止了与输入地址信号的不期望的电平变化有关的错误操作，并且确保了主放大器的适当的操作。 半导体存储器件具有主放大器激活脉冲发生器112'，其包括响应灵敏度降低电路10，响应灵敏度选择器12和主放大器激活脉冲发生器14.响应灵敏度降低电路10可以降低响应灵敏度降低电路10的响应灵敏度或输入灵敏度 电路112'相对于输入地址转换检测脉冲ATD。 响应灵敏度选择器12根据主放大器激活脉冲发生器14的输出状态选择第一输入端子A1或第二输入端子A2。因此，当没有主放大器从主振荡器激活脉冲MA的输出 放大器激活脉冲发生器14，响应灵敏度选择器12切换到第一输入端子A1以选择响应灵敏度降低电路10; 当输出主放大器激活脉冲MA时，选择器12切换到第二输入端A2以选择旁路电路11。

公开(公告)号：US5761149A

公开(公告)日：1998-06-02

申请号：US679724

申请日：1996-07-12

申请人： Yukihide Suzuki ,  Kanehide Kenmizaki ,  Tsugio Takahashi ,  Masayuki Nakamura ,  Makoto Saeki ,  Chisa Makimura ,  Katsuo Komatsuzaki ,  Shunichi Sukegawa

发明人： Yukihide Suzuki ,  Kanehide Kenmizaki ,  Tsugio Takahashi ,  Masayuki Nakamura ,  Makoto Saeki ,  Chisa Makimura ,  Katsuo Komatsuzaki ,  Shunichi Sukegawa

IPC分类号： H01L27/108 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/418 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8242 ,  H01L27/105 ,  G11C8/00

CPC分类号： G11C29/80 ,  G11C11/418 ,  G11C29/83 ,  G11C8/14 ,  H01L27/105

摘要： A dynamic RAM is provided with a main word lines; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which are extended so as to perpendicularly intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the dynamic RAM, the voltage level of each of the main word line and the subsidiary word selection lines is made to be equal to the ground potential when the line is in a not-selected state.

摘要翻译： 动态RAM具有主字线; 多个辅助字线，沿着与主字线交叉的位线的方向排列，多个动态存储单元被连接到该多个辅助字线; 多个副字选择线，其被延伸成与主字线垂直相交，并且通过该多个副字选择线发送用于选择多个辅助字线中的一个的选择信号; 以及用于从主字线接收选择信号的逻辑电路和来自每个辅助字选择线的选择信号，从而形成用于选择一个辅助字线的选择信号。 在动态RAM中，当线处于未选择状态时，使主字线和副字选择线中的每一个的电压电平等于地电位。

公开(公告)号：US5844915A

公开(公告)日：1998-12-01

申请号：US716080

申请日：1996-09-19

申请人： Yoritaka Saitoh ,  Shunichi Sukegawa ,  Makoto Saeki ,  Yukihide Suzuki

发明人： Yoritaka Saitoh ,  Shunichi Sukegawa ,  Makoto Saeki ,  Yukihide Suzuki

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C11/401

摘要： A word line leak check test for a semiconductor memory arranged as a matrix which includes word lines and y-selection lines. First, a RAS signal is enabled while a prescribed row address is input, and word line 22 is driven to the Vpp level. Then, when the CAS signal is enabled, the voltage source is disconnected from word line 22, and word line 22 floats. Two bits for the column address are disregarded, and the Y selection signal line 23 is decoded without those 2 bits. By this means, 4 y-selection signal lines 23 are simultaneously enabled. When this condition has been maintained for a prescribed time T, a delayed write operation is conducted, and then it is determined whether the data has been correctly stored in memory cell 24.

摘要翻译： 布置为包括字线和y选择线的矩阵的半导体存储器的字线泄漏检查测试。 首先，在输入规定的行地址的同时使能RAS信号，将字线22驱动到Vpp电平。 然后，当CAS信号被使能时，电压源与字线22断开，字线22浮起。 忽略列地址的两位，并且Y选择信号线23被解码而没有那些2位。 通过这种方式，同时使能4个y选择信号线23。 当该条件保持规定时间T时，进行延迟写入操作，然后确定数据是否已被正确存储在存储单元24中。

公开(公告)号：US5805522A

公开(公告)日：1998-09-08

申请号：US706373

申请日：1996-08-30

申请人： Shunichi Sukegawa ,  Koichi Abe ,  Makoto Saeki ,  Yukihide Suzuki

发明人： Shunichi Sukegawa ,  Koichi Abe ,  Makoto Saeki ,  Yukihide Suzuki

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1048

摘要： An address access path control circuit designed for shorter access time and small the layout area with low power consumption and noise. Our control circuit has a latching circuit LMO2A, a main output circuit MO3, and a common-bus driving circuit CBD for holding the level of a pair of common-buses CB/CB.sub.-- at the ground level during a prescribed period of time in which address transition takes place while the read data is output to common-buses CB/CB.sub.-- at a timing corresponding to the address signal. A data output buffer DO-BUF outputs to the outside the data transmitted from common-buses CB/CB.sub.-- to data output lines OD/OD.sub.-- in response to the input of control signal DOE. A control signal DOE is input to data output buffer DO-BUF during the period in which data output lines OD/OD.sub.-- are at the ground level.

摘要翻译： 一种地址访问路径控制电路，设计用于更短的访问时间，并且具有低功耗和噪声的布局区域较小。 我们的控制电路有一个锁存电路LMO2A，一个主输出电路MO3和一个共用总线驱动电路CBD，用于在一段规定的时间内保持一对公共汽车CB / CB-的电平， 在与地址信号相对应的定时将读取数据输出到公共总线CB / CB-时发生地址转换。 响应于控制信号DOE的输入，数据输出缓冲器DO-BUF向外部输出从公共总线CB / CB-发送到数据输出线OD / OD-的数据。 在数据输出线OD / OD-处于地电平的期间，控制信号DOE输入到数据输出缓冲器DO-BUF。

公开(公告)号：US5892726A

公开(公告)日：1999-04-06

申请号：US721294

申请日：1996-09-26

申请人： Yoojoon Moon ,  Shunichi Sukegawa ,  Yasuhito Ichimura ,  Makoto Saeki

发明人： Yoojoon Moon ,  Shunichi Sukegawa ,  Yasuhito Ichimura ,  Makoto Saeki

IPC分类号： G11C11/413 ,  G11C8/10 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C8/10 ,  G11C11/4087

摘要： An address decoder with low power consumption of feedthrough current, leakage current, etc. Address bits AY0.sub.0 -AY0.sub.7 are respectively supplied to n-type gate terminals of CMOS transfer gates C.sub.0 -C.sub.7 and the gate terminals of PMOS transistors P.sub.0 -P.sub.7. Inverted address bits AY0.sub.0- -AY0.sub.7- are supplied to p-type gate terminals of the CMOS transfer gates C.sub.0 -C.sub.7. Enable signals AY3.sub.p, AY6.sub.q are respectively input to both input terminals of a NAND circuit 10. The output terminals of NAND circuit 10 are connected to the input terminals of CMOS transfer gates C.sub.0 -C.sub.7. The output terminals of CMOS transfer gates C.sub.0 -C.sub.7 are connected to the input terminals of the drivers D.sub.0 -D.sub.7 and the drain terminals of the PMOS transistors P.sub.0 -P.sub.7 via a node F.sub.0 -F.sub.7. The source terminals of PMOS transistors P.sub.0 -P.sub.7 are connected to a power supply voltage V.sub.cc, for example of 3.3 V. The output terminals of drivers D.sub.0 -D.sub.7 are connected to Y-address lines YS.sub.0 -YS.sub.7.

摘要翻译： 具有低通电电流，漏电流等功耗的地址解码器。地址位AY00-AY07分别提供给CMOS传输门C0-C7的n型栅极端子和PMOS晶体管P0-P7的栅极端子。 反向地址位AY00 - AY07-被提供给CMOS传输门C0-C7的p型栅极端子。 分别向NAND电路10的两个输入端子输入使能信号AY3p，AY6q。NAND电路10的输出端子与CMOS转移门C0-C7的输入端子连接。 CMOS传输门C0-C7的输出端通过节点F0-F7连接到驱动器D0-D7的输入端和PMOS晶体管P0-P7的漏极端子。 PMOS晶体管P0-P7的源极端子连接到例如3.3V的电源电压Vcc。驱动器D0-D7的输出端子连接到Y地址线YS0-YS7。

公开(公告)号：US5629898A

公开(公告)日：1997-05-13

申请号：US607977

申请日：1996-02-29

申请人： Youji Idei ,  Katsuhiro Shimohigashi ,  Masakazu Aoki ,  Hiromasa Noda ,  Katsuyuki Sato ,  Hidetoshi Iwai ,  Makoto Saeki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Osamu Tsuchiya

发明人： Youji Idei ,  Katsuhiro Shimohigashi ,  Masakazu Aoki ,  Hiromasa Noda ,  Katsuyuki Sato ,  Hidetoshi Iwai ,  Makoto Saeki ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Osamu Tsuchiya

IPC分类号： G11C11/406 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4016 ,  G11C2211/4061

摘要： A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.

摘要翻译： 对与动态存储单元的最短信息保持时间对应的周期脉冲进行计数，以形成分配给多个字线的刷新地址。 从刷新地址计数器输出的进位信号由分频器分频。 对于分配有刷新地址的所述多个字线中的每一个，对应于定时器的输出脉冲的短周期中的一个或与来自分频器的分频脉冲相对应的长周期中的一个作为刷新时间设置信息被存储在存储电路中 。 根据存储在存储电路中的刷新时间设定信息，由刷新地址执行的存储器单元刷新动作对每个字线进行有效或无效，并且刷新时间设定信息本身被分频器的输出脉冲无效 。

公开(公告)号：US5726967A

公开(公告)日：1998-03-10

申请号：US654721

申请日：1996-05-29

申请人： Shinsaku Tanaka ,  Tadao Arata ,  Akira Iwakiri ,  Makoto Saeki

发明人： Shinsaku Tanaka ,  Tadao Arata ,  Akira Iwakiri ,  Makoto Saeki

IPC分类号： G11B17/22 ,  G11B17/26 ,  G11B17/10 ,  G11B17/04

CPC分类号： G11B17/223 ,  G11B17/26

摘要： A disk playback apparatus comprises a stocker including a plurality of shelves for compact disks, a pallet disposed adjacent to the stocker, a lift stage for moving the stocker up and down so that a selected one of the shelves is located in a position higher than the pallet for a predetermined distance, a loader capable of reciprocating between an unloading position on the stocker side and a loading position on the pallet side, and a lifter in the loader. As the loader moves from the unloading position toward the loading position, the lifter lowers and feeds the disk on the selected shelf to the pallet while drawing out the disk from the stocker. As the loader moves from the loading position toward the unloading position, the lifter raises and returns the disk on the pallet to the selected shelf while pushing back the disk toward the stocker.

摘要翻译： 一种盘播放装置包括一个储盘器，该贮存器包括用于光盘的多个搁架，与该储盘器相邻设置的托盘，用于上下移动该储盘架的升降台，使得所选择的一个搁板位于高于 托盘预定距离，能够在储料器侧的卸载位置和托盘侧的装载位置之间往复运动的装载机和装载机中的升降机。 当装载机从卸载位置移动到装载位置时，升降器降低并将所选择的货架上的盘送入托盘，同时从储料器中拉出盘。 当装载机从装载位置移动到卸载位置时，提升器将托盘上的盘返回到选定的货架上，同时将盘向储盘器推回。

公开(公告)号：US5345421A

公开(公告)日：1994-09-06

申请号：US905745

申请日：1992-06-29

申请人： Masahiro Iwamura ,  Tatsumi Yamauchi ,  Makoto Saeki ,  Hideaki Uchida

发明人： Masahiro Iwamura ,  Tatsumi Yamauchi ,  Makoto Saeki ,  Hideaki Uchida

IPC分类号： G11C11/417 ,  G11C11/401 ,  G11C11/409 ,  H03K19/003 ,  H03K19/00

CPC分类号： H03K19/00361

摘要： A wide-bit output semiconductor storage device of high speed and low noise is provided in which output circuits are grouped into two groups and the two output circuit groups are so controlled as to be switched in directions of levels which are opposite to each other.

摘要翻译： 提供了一种高速和低噪声的宽位输出半导体存储器件，其中输出电路被分组成两组，并且两个输出电路组被如此控制以在彼此相反的电平的方向上切换。

公开(公告)号：US5543652A

公开(公告)日：1996-08-06

申请号：US98893

申请日：1993-07-29

申请人： Shuji Ikeda ,  Makoto Saeki

发明人： Shuji Ikeda ,  Makoto Saeki

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L29/88 ,  H01L27/01 ,  H01L29/76

CPC分类号： H01L29/78696 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

摘要： Negative characteristic MISFETs, which are of the same channel conductivity type and which have different threshold voltages, are formed in a doped silicon thin film deposited over a substrate and are connected in channel-to-channel series with each other. The pair of series-connected negative characteristic MISFETs, a resistive element, an information storage capacitive element and a transfer MISFET constitute an SRAM memory cell. Equivalently, a negative characteristic MISFET having a current-voltage characteristic defined by a negative resistance curve can be used in lieu of the pair of series-connected negative characteristic MISFETs in the formation of the individual memory cells of the SRAM. The negative resistance curve of the negative characteristic MISFET is shaped such that the linear current-voltage characteristic curve corresponding to the resistive element of the memory cell intersects the negative resistance curve at at least three location points. The negative characteristic MISFET, like the pair of series-connected negative characteristic MISFETs, has an active region formed in a doped thin film silicon (polycrystalline silicon) layer insulatedly above a substrate main surface. The resistive element is also formed in a thin film silicon layer either integrally with the negative characteristic MISFET or in a separate thin film silicon layer and in series electrical connection with the negative characteristic MISFET.

摘要翻译： 具有相同沟道导电类型且具有不同阈值电压的负特性MISFET形成在沉积在衬底上并以通道间通道串联连接的掺杂硅薄膜中。 一对串联负特性MISFET，电阻元件，信息存储电容元件和转移MISFET构成SRAM存储单元。 等效地，可以使用由负电阻曲线限定的电流 - 电压特性的负特性MISFET来代替在SRAM的各个存储单元的形成中的一对串联负特性MISFET。 负特性MISFET的负电阻曲线被成形为使得对应于存储单元的电阻元件的线性电流 - 电压特性曲线在至少三个位置点处与负电阻曲线相交。 负极特性MISFET，像一对串联连接的负特性MISFET一样，具有在衬底主表面上绝缘的掺杂薄膜硅（多晶硅）层中形成的有源区。 电阻元件也与负特性MISFET或单独的薄膜硅层整体地形成在薄膜硅层中，并与负特性MISFET串联电连接。

公开(公告)号：US4876669A

公开(公告)日：1989-10-24

申请号：US203459

申请日：1988-06-07

申请人： Sho Yamamoto ,  Osamu Minato ,  Makoto Saeki ,  Yasuo Yoshitomi ,  Hideaki Nakamura ,  Masaaki Kubotera

发明人： Sho Yamamoto ,  Osamu Minato ,  Makoto Saeki ,  Yasuo Yoshitomi ,  Hideaki Nakamura ,  Masaaki Kubotera

IPC分类号： G11C11/417 ,  G11C11/34 ,  G11C11/419

CPC分类号： G11C11/419

摘要： An MOS static type RAM has a memory cell array comprising of a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals of the respective memory cells. Data line load circuits are disposed between the power terminal of the circuit and the data lines. Each data line load circuit is kept at a relatively high impedance in the data write-in operation, and at a relatively low impedance in the data read-out operation. The use of the data line load circuits comprised of such variable impedance circuits can speed up the operating speed of the RAM and can accomplish lower power consumption.

摘要翻译： MOS静态型RAM具有存储单元阵列，其包括以矩阵形式排列的多个静态型存储单元，连接到各个存储单元的数据输入 - 输出端的多条数据线以及与该存储单元连接的多条字线 各个存储单元的选择端。 数据线负载电路设置在电路的电源端子和数据线之间。 每个数据线路负载电路在数据写入操作中保持相对高的阻抗，并且在数据读出操作中处于相对较低的阻抗。 由这种可变阻抗电路构成的数据线负载电路的使用可以加速RAM的工作速度并且可以实现更低的功耗。