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公开(公告)号：US08953397B2
公开(公告)日：2015-02-10
申请号：US13601609
申请日：2012-08-31
申请人： Tai Kyu Kang , Sang Hyun Song
发明人： Tai Kyu Kang , Sang Hyun Song
CPC分类号： G11C16/225 , G11C16/06 , G11C16/32
摘要： The present disclosure relates to a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a ROM for storing a program algorithm, an erase algorithm, a reading algorithm, and a reset algorithm and outputting ROM data corresponding to a selected algorithm, a program counter for outputting a ROM address to the ROM so as to sequentially operate the selected algorithm, an internal circuit for performing an operation corresponding to the selected algorithm in response to a plurality of internal circuit control signals in response to the ROM data, and a reset circuit for stopping progress of a running algorithm by initializing the program counter in response to a reset command input from an outside, and performing the reset algorithm.
摘要翻译： 本公开涉及半导体器件和操作半导体器件的方法。 半导体器件包括用于存储程序算法的ROM，擦除算法，读取算法和复位算法，并且输出与所选择的算法相对应的ROM数据，用于向ROM输出ROM地址以便顺序操作的程序计数器 所选择的算法，响应于ROM数据而响应于多个内部电路控制信号执行与所选算法对应的操作的内部电路，以及用于通过初始化程序计数器来停止运行算法的进展的复位电路 响应于从外部输入的复位命令，并执行复位算法。
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公开(公告)号：US20120008393A1
公开(公告)日：2012-01-12
申请号：US12974330
申请日：2010-12-21
申请人： Jung-Chul HAN , Tai-Kyu Kang
发明人： Jung-Chul HAN , Tai-Kyu Kang
CPC分类号： G11C16/3418 , G11C16/14
摘要： An operation method of a nonvolatile memory device includes reading information of an erase target block, and performing an erase operation by using a starting erase bias corresponding to the information.
摘要翻译： 非易失性存储器件的操作方法包括读取擦除目标块的信息，并且通过使用与该信息对应的起始擦除偏置来执行擦除操作。
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3.发明申请公开(公告)号：US20080084766A1
公开(公告)日：2008-04-10
申请号：US11617670
申请日：2006-12-28
申请人： Min Joong Jung , Byoung Kwan Jeong , Tai Kyu Kang
发明人： Min Joong Jung , Byoung Kwan Jeong , Tai Kyu Kang
CPC分类号： G11C16/16 , H01L2924/0002 , H01L2924/00
摘要： A flash memory device comprises a memory cell array having a plurality of blocks. An address register section is configured to receive a start block address of the first block to be erased among a plurality of blocks to be erased and a last block address of the last block to be erased among the plurality of blocks to be erased. A controlling logic circuit is configured to output an erase command signal and an erase block address corresponding to one of the blocks to be erased. A block address comparing section is configured to compare the erase block address output by the controlling logic circuit with the last block address, and output an erase progress signal based on the comparison of the erase block address and the last block address to the controlling logic circuit. The controlling logic circuit outputs an erase block address of to another block to be erased until the erase progress signal indicates that the last block to be erased has been or is being erased.
摘要翻译： 闪存器件包括具有多个块的存储单元阵列。 地址寄存器部分被配置为在要擦除的多个块中接收要擦除的第一块的起始块地址和要擦除的多个块中要擦除的最后块的最后块地址。 控制逻辑电路被配置为输出与要擦除的块中的一个对应的擦除命令信号和擦除块地址。 块地址比较部分被配置为将由控制逻辑电路输出的擦除块地址与最后的块地址进行比较，并且基于擦除块地址和最后块地址的比较将控制逻辑电路输出擦除进行信号 。 控制逻辑电路输出要擦除的另一个块的擦除块地址，直到擦除进度信号指示要擦除的最后一个块已经或正被擦除。
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公开(公告)号：US20100290288A1
公开(公告)日：2010-11-18
申请号：US12702597
申请日：2010-02-09
申请人： Tai Kyu Kang
发明人： Tai Kyu Kang
CPC分类号： G11C29/44 , G11C16/04 , G11C29/4401 , G11C29/72
摘要： A nonvolatile memory device includes a storage unit configured to store pattern data selected based on a test command set, and a control unit configured to consecutively perform a program operation on a number of pages in response to the pattern data to obtain programmed pages, consecutively perform a read operation on the programmed pages, and provide information about a bit line coupled to a fail memory cell and about a number of fail bit lines checked as a result of the read operation.
摘要翻译： 非易失性存储装置包括：存储单元，被配置为存储基于测试命令集选择的模式数据;以及控制单元，被配置为响应于模式数据连续执行对多个页面的编程操作以获得编程页面，连续执行 对所编程的页面进行读取操作，并提供关于耦合到故障存储器单元的位线和作为读取操作的结果检查的大量故障位线的信息。
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公开(公告)号：US20100214853A1
公开(公告)日：2010-08-26
申请号：US12647576
申请日：2009-12-28
申请人： Tai Kyu Kang
发明人： Tai Kyu Kang
摘要： A nonvolatile memory device includes a control unit configured to measure a threshold voltage distribution of each of selected pages between a start voltage and an end voltage by performing a read operation on each page in response to a command set for analyzing the threshold voltage distribution, to compare the measured threshold voltage distribution with a reference threshold voltage distribution, and to determine a read voltage having a least amount of errors upon the read operation being performed.
摘要翻译： 非易失性存储器件包括：控制单元，被配置为响应于用于分析阈值电压分布的命令集，通过对每个页面执行读取操作来测量在开始电压和结束电压之间的每个选定页面的阈值电压分布， 将测量的阈值电压分布与参考阈值电压分布进行比较，并且在执行读取操作时确定具有最小误差量的读取电压。
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6.发明授权公开(公告)号：US07684254B2
公开(公告)日：2010-03-23
申请号：US11617670
申请日：2006-12-28
申请人： Min Joong Jung , Byoung Kwan Jeong , Tai Kyu Kang
发明人： Min Joong Jung , Byoung Kwan Jeong , Tai Kyu Kang
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , H01L2924/0002 , H01L2924/00
摘要： A flash memory device comprises a memory cell array having a plurality of blocks. An address register section is configured to receive a start block address of the first block to be erased among a plurality of blocks to be erased and a last block address of the last block to be erased among the plurality of blocks to be erased. A controlling logic circuit is configured to output an erase command signal and an erase block address corresponding to one of the blocks to be erased. A block address comparing section is configured to compare the erase block address output by the controlling logic circuit with the last block address, and output an erase progress signal based on the comparison of the erase block address and the last block address to the controlling logic circuit. The controlling logic circuit outputs an erase block address of to another block to be erased until the erase progress signal indicates that the last block to be erased has been or is being erased.
摘要翻译： 闪存器件包括具有多个块的存储单元阵列。 地址寄存器部分被配置为在要擦除的多个块中接收要擦除的第一块的起始块地址和要擦除的多个块中要擦除的最后块的最后块地址。 控制逻辑电路被配置为输出与要擦除的块中的一个对应的擦除命令信号和擦除块地址。 块地址比较部分被配置为将由控制逻辑电路输出的擦除块地址与最后的块地址进行比较，并且基于擦除块地址和最后块地址的比较将控制逻辑电路输出擦除进行信号 。 控制逻辑电路输出要擦除的另一个块的擦除块地址，直到擦除进度信号指示要擦除的最后一个块已经或正被擦除。
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公开(公告)号：US08576621B2
公开(公告)日：2013-11-05
申请号：US12647576
申请日：2009-12-28
申请人： Tai Kyu Kang
发明人： Tai Kyu Kang
IPC分类号： G11C11/34
摘要： A nonvolatile memory device includes a control unit configured to measure a threshold voltage distribution of each of selected pages between a start voltage and an end voltage by performing a read operation on each page in response to a command set for analyzing the threshold voltage distribution, to compare the measured threshold voltage distribution with a reference threshold voltage distribution, and to determine a read voltage having a least amount of errors upon the read operation being performed.
摘要翻译： 非易失性存储器件包括：控制单元，被配置为响应于用于分析阈值电压分布的命令集，通过对每个页面执行读取操作来测量在开始电压和结束电压之间的每个选定页面的阈值电压分布， 将测量的阈值电压分布与参考阈值电压分布进行比较，并且在执行读取操作时确定具有最小误差量的读取电压。
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公开(公告)号：US20130107647A1
公开(公告)日：2013-05-02
申请号：US13601609
申请日：2012-08-31
申请人： Tai Kyu KANG , Sang Hyun SONG
发明人： Tai Kyu KANG , Sang Hyun SONG
IPC分类号： G11C7/00
CPC分类号： G11C16/225 , G11C16/06 , G11C16/32
摘要： The present disclosure relates to a semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a ROM for storing a program algorithm, an erase algorithm, a reading algorithm, and a reset algorithm and outputting ROM data corresponding to a selected algorithm, a program counter for outputting a ROM address to the ROM so as to sequentially operate the selected algorithm, an internal circuit for performing an operation corresponding to the selected algorithm in response to a plurality of internal circuit control signals in response to the ROM data, and a reset circuit for stopping progress of a running algorithm by initializing the program counter in response to a reset command input from an outside, and performing the reset algorithm.
摘要翻译： 本公开涉及半导体器件和操作半导体器件的方法。 半导体器件包括用于存储程序算法的ROM，擦除算法，读取算法和复位算法，并且输出与所选择的算法相对应的ROM数据，用于向ROM输出ROM地址以便顺序操作的程序计数器 所选择的算法，响应于ROM数据而响应于多个内部电路控制信号执行与所选算法对应的操作的内部电路，以及用于通过初始化程序计数器来停止运行算法的进展的复位电路 响应于从外部输入的复位命令，并执行复位算法。
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公开(公告)号：US08159892B2
公开(公告)日：2012-04-17
申请号：US12702597
申请日：2010-02-09
申请人： Tai Kyu Kang
发明人： Tai Kyu Kang
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C16/04 , G11C29/4401 , G11C29/72
摘要： A nonvolatile memory device includes a storage unit configured to store pattern data selected based on a test command set, and a control unit configured to consecutively perform a program operation on a number of pages in response to the pattern data to obtain programmed pages, consecutively perform a read operation on the programmed pages, and provide information about a bit line coupled to a fail memory cell and about a number of fail bit lines checked as a result of the read operation.
摘要翻译： 非易失性存储装置包括：存储单元，被配置为存储基于测试命令集选择的模式数据;以及控制单元，被配置为响应于模式数据连续执行对多个页面的编程操作以获得编程页面，连续执行 对所编程的页面进行读取操作，并提供关于耦合到故障存储器单元的位线和作为读取操作的结果检查的大量故障位线的信息。
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