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1.发明授权Method of manufacturing semiconductor device having impurity region under isolation region 有权制造在隔离区域具有杂质区域的半导体器件的制造方法公开(公告)号：US07556997B2
公开(公告)日：2009-07-07
申请号：US11907864
申请日：2007-10-18
IPC分类号： H01L21/8238
CPC分类号： H01L29/78615 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film prevents a well region located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
摘要翻译： 在形成NMOS晶体管的源极/漏极区域中，N +块抗蚀剂膜51中的N +块区域41的栅极延伸区域<41a>防止位于栅极下方的阱区域11 从N型杂质的注入开始的方向延伸区域41a。 可以形成具有在栅电极9的纵向延伸上注入N型杂质的可能性的具有高电阻形成区域
的高电阻形成区域， 比传统的高电阻形成区域 。 因此，获得具有能够降低体电阻的部分隔离体固定的SOI结构的半导体器件及其制造方法。 -
2.发明授权Semiconductor device having a trench isolation and method of fabricating the same 失效具有沟槽隔离的半导体器件及其制造方法公开(公告)号：US07494883B2
公开(公告)日：2009-02-24
申请号：US11543213
申请日：2006-10-05
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60〜120keV，通道阻挡层的密度为1×10 17〜1×10 19 / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。
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3.发明授权Method of manufacturing semiconductor device having impurity region under isolation region 失效制造在隔离区域具有杂质区域的半导体器件的制造方法公开(公告)号：US07470582B2
公开(公告)日：2008-12-30
申请号：US11907857
申请日：2007-10-18
IPC分类号： H01L21/8238
CPC分类号： H01L29/78615 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film prevents a well region located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
摘要翻译： 在形成NMOS晶体管的源极/漏极区域中，N +块抗蚀剂膜51中的N +块区域41的栅极延伸区域<41a>防止位于栅极下方的阱区域11 从N型杂质的注入开始的方向延伸区域41a。 可以形成具有在栅电极9的纵向延伸上注入N型杂质的可能性的具有高电阻形成区域
的高电阻形成区域， 比传统的高电阻形成区域 。 因此，获得具有能够降低体电阻的部分隔离体固定SOI结构的半导体器件及其制造方法。 -
4.发明申请Method of manufacturing semiconductor device having impurity region under isolation region 有权制造在隔离区域具有杂质区域的半导体器件的制造方法公开(公告)号：US20070034952A1
公开(公告)日：2007-02-15
申请号：US11493529
申请日：2006-07-27
CPC分类号： H01L29/78615 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film prevents a well region located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
摘要翻译： 在形成NMOS晶体管的源极/漏极区域的情况下，在N + +块区域中的N + +块区域<41>的栅极方向延伸区域 抗蚀剂膜<51>防止位于栅极方向延伸区域41a之下的阱区11注入N型杂质。 作为高电阻形成区域，其是具有在栅电极9的纵向延伸上注入N型杂质的可能性的阱区域11，可以形成为高电阻形成区域 比传统的高电阻形成区域窄。 因此，获得具有能够降低体电阻的部分隔离体固定的SOI结构的半导体器件及其制造方法。
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公开(公告)号：US07173319B2
公开(公告)日：2007-02-06
申请号：US11002142
申请日：2004-12-03
申请人： Toshiaki Iwamatsu , Takashi Ipposhi
发明人： Toshiaki Iwamatsu , Takashi Ipposhi
IPC分类号： H01L29/80 , H01L31/112 , H01L27/082
CPC分类号： H01L27/0617 , H01L21/76283 , H01L21/84 , H01L27/0629 , H01L27/1203 , H01L27/13 , H01L28/10 , H01L28/20 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Plural trench isolation films (4) are provided with portions of an SOI layer (3) interposed therebetween in a surface of the SOI layer (3) in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element (30) are formed on the trench isolation films (4), respectively. Each of the trench isolation films (4) includes a central portion which passes through the SOI layer (3) and reaches a buried oxide film (2) to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer (3) and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films (4) includes a hybrid-trench isolation structure.
摘要翻译： 多个沟槽隔离膜（4）在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层（3）的表面中设置有SOI层（3）的部分。 电阻元件（30）分别形成在沟槽隔离膜（4）上。 每个沟槽隔离膜（4）包括通过SOI层（3）并到达掩埋氧化膜（2）以包括全沟槽隔离结构的中心部分，并且每个沟道隔离膜仅穿过 SOI层（3）的一部分并且位于SOI层3上以包括部分沟槽隔离结构。 因此，每个沟槽隔离膜（4）包括混合沟槽隔离结构。
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公开(公告)号：US20060270126A1
公开(公告)日：2006-11-30
申请号：US11500340
申请日：2006-08-08
申请人： Toshiaki Iwamatsu , Takashi Ipposhi
发明人： Toshiaki Iwamatsu , Takashi Ipposhi
CPC分类号： H01L27/0617 , H01L21/76283 , H01L21/84 , H01L27/0629 , H01L27/1203 , H01L27/13 , H01L28/10 , H01L28/20 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.
摘要翻译： 多个沟槽隔离膜在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层的表面中设置有SOI层的部分。 电阻元件分别形成在沟槽隔离膜上。 每个沟槽隔离膜包括穿过SOI层并到达掩埋氧化膜以包括全沟槽隔离结构的中心部分，以及相对的侧部，其每个仅穿过SOI层的一部分并且位于 在SOI层3上，以包括部分沟槽隔离结构。 因此，每个沟槽隔离膜包括混合沟槽隔离结构。
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公开(公告)号：US07067881B2
公开(公告)日：2006-06-27
申请号：US10754539
申请日：2004-01-12
IPC分类号： H01L27/01
CPC分类号： H01L29/66545 , H01L21/28052 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/41766 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834 , H01L29/7845
摘要： A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.
摘要翻译： 提供一种半导体器件及其制造方法，其可以适当地避免隔离击穿电压的降低，而不会引起诸如结电容增加的不利影响。 在通过形成凹部（14）使硅层（3）变薄之后形成杂质导入区域（11）。 因此，在位于元件隔离绝缘膜（5）的底部和BOX层（2）的顶面之间的p型硅层（3）的部分中不会注入n型杂质，避免了还原 的隔离击穿电压。 此外，由于杂质引入区域（11）形成为到达BOX层（2）的上表面，所以源极/漏极区域（12）的结电容不增加。
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公开(公告)号：US20050167673A1
公开(公告)日：2005-08-04
申请号：US11078581
申请日：2005-03-14
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L21/265 , H01L21/336 , H01L27/11 , H01L27/12 , H01L29/417 , H01L29/45 , H01L29/786 , H01L29/04
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译： 提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。 漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。 漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。 定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。
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公开(公告)号：US20050156242A1
公开(公告)日：2005-07-21
申请号：US11034938
申请日：2005-01-14
申请人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
发明人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
IPC分类号： H01L21/762 , H01L21/331 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L31/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
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10.发明申请Semiconductor device having a trench isolation and method of fabricating the same 失效具有沟槽隔离的半导体器件及其制造方法公开(公告)号：US20050101091A1
公开(公告)日：2005-05-12
申请号：US11011655
申请日：2004-12-15
IPC分类号： H01L21/76 , H01L21/336 , H01L21/762 , H01L21/84 , H01L27/08 , H01L27/12 , H01L29/786 , H01L21/8242 , H01L21/8234
CPC分类号： H01L21/2652 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60至120keV，并且通道阻挡层的密度设定为1×10 17至1×10 19 / SUP> / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。
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