公开(公告)号：US07852111B2

公开(公告)日：2010-12-14

申请号：US12409838

申请日：2009-03-24

申请人： Takashi Oguri

发明人： Takashi Oguri

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  H03K17/163 ,  H03K19/017581

摘要： A 4-bit counter outputs a 4-bit counted value CNTp based on an up-and-down signal Sp supplied from a comparator. A weighting selection circuit performs weighting based on a deviation from an average value of the DC characteristic of each PMOS transistor, and assigns a transistor having the smallest deviation to Bit 1 (LSB) of the 4-bit counter. The weighting selection circuit assigns two PMOS transistors to Bit 2 of the 4-bit counter, four PMOS transistors to Bit 3, and eight PMOS transistors to Bit 4 (MSB). Then, the weighting selection circuit selects transistors P3-1 to P3-30 based on the counted value CNTp output from the 4-bit counter.

摘要翻译： 4位计数器基于从比较器提供的上下降信号Sp输出4位计数值CNTp。 加权选择电路根据与每个PMOS晶体管的DC特性的平均值的偏差进行加权，并将具有最小偏差的晶体管分配给4位计数器的位1（LSB）。 加权选择电路将两个PMOS晶体管分配给4位计数器的位2，将4个PMOS晶体管分配给位3，将8个PMOS晶体管分配到位4（MSB）。 然后，加权选择电路基于从4位计数器输出的计数值CNTp选择晶体管P3-1至P3-30。

公开(公告)号：US06828829B2

公开(公告)日：2004-12-07

申请号：US10437174

申请日：2003-05-14

申请人： Takashi Oguri

发明人： Takashi Oguri

IPC分类号： H03K5153

CPC分类号： H03K19/1732 ,  H03K19/018514

摘要： A semiconductor device is constructed by at least one reference voltage generating circuit for generating a reference voltage, a plurality of input voltage pads for receiving input voltages, a control signal pad for receiving a control signal, and a plurality of input buffers. Each of the input buffers amplifies a difference between one of the input voltages and the reference voltage to generate an output voltage, and includes a switch connected between the reference voltage generating circuit and one of the input voltage pads and controlled by the control signal.

摘要翻译： 半导体器件由用于产生参考电压的至少一个参考电压产生电路，用于接收输入电压的多个输入电压焊盘，用于接收控制信号的控制信号焊盘和多个输入缓冲器构成。 每个输入缓冲器放大一个输入电压和参考电压之间的差以产生输出电压，并且包括连接在参考电压产生电路和其中一个输入电压焊盘之间并由控制信号控制的开关。

公开(公告)号：US5357154A

公开(公告)日：1994-10-18

申请号：US960814

申请日：1992-10-14

申请人： Takashi Oguri

发明人： Takashi Oguri

IPC分类号： H03K19/0175 ,  H03K19/08 ,  H03K19/01

CPC分类号： H03K19/017518

摘要： A level converter circuit, in which a bipolar transistor for raising an output voltage is switched on or off by a logical-BiMIS construction, and a MIS transistor for falling the output voltage is also switched on or off by a logic circuit and a charge discharge means 50 so as to reduce a propagation delay time, to raise a driving ability, to prevent a steady state current and to reduce a dissipation current.

摘要翻译： 通过逻辑BiMIS结构将用于提高输出电压的双极晶体管接通或关断的电平转换器电路，并且用于降低输出电压的MIS晶体管也通过逻辑电路和充电放电来接通或断开 装置50，以减少传播延迟时间，提高驱动能力，防止稳态电流并减少耗散电流。

公开(公告)号：US20090256586A1

公开(公告)日：2009-10-15

申请号：US12409838

申请日：2009-03-24

申请人： TAKASHI OGURI

发明人： TAKASHI OGURI

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  H03K17/163 ,  H03K19/017581

摘要： A 4-bit counter outputs a 4-bit counted value CNTp based on an up-and-down signal Sp supplied from a comparator. A weighting selection circuit performs weighting based on a deviation from an average value of the DC characteristic of each PMOS transistor, and assigns a transistor having the smallest deviation to Bit 1 (LSB) of the 4-bit counter. The weighting selection circuit assigns two PMOS transistors to Bit 2 of the 4-bit counter, four PMOS transistors to Bit 3, and eight PMOS transistors to Bit 4 (MSB). Then, the weighting selection circuit selects transistors P3-1 to P3-30 based on the counted value CNTp output from the 4-bit counter.

摘要翻译： 4位计数器基于从比较器提供的上下降信号Sp输出4位计数值CNTp。 加权选择电路根据与每个PMOS晶体管的DC特性的平均值的偏差进行加权，并将具有最小偏差的晶体管分配给4位计数器的位1（LSB）。 加权选择电路将两个PMOS晶体管分配给4位计数器的位2，将4个PMOS晶体管分配给位3，将8个PMOS晶体管分配到位4（MSB）。 然后，加权选择电路基于从4位计数器输出的计数值CNTp选择晶体管P3-1至P3-30。

公开(公告)号：US06236255B1

公开(公告)日：2001-05-22

申请号：US09200476

申请日：1998-11-27

申请人： Takashi Oguri

发明人： Takashi Oguri

IPC分类号： H03B100

CPC分类号： H03K19/00384 ,  H03K19/0005

摘要： An output circuit has an n-channel constant voltage circuit and p-channel constant voltage circuit. The output circuit includes a p-channel MOS transistor and an n-channel MOS transistor at the output stage thereof. The n-channel constant voltage circuit controls the drive of the p-channel MOS transistor, and causes current flowing through the p-channel MOS transistor so that current path through the p-channel MOS transistor to be constant or substantially constant. The p-channel constant voltage circuit controls the drive of the n-channel MOS transistor, and causes current flowing through the n-channel MOS transistor so that current path through the n-channel MOS transistor to be constant or substantially constant.

摘要翻译： 输出电路具有n沟道恒压电路和p沟道恒压电路。 输出电路包括在其输出级的p沟道MOS晶体管和n沟道MOS晶体管。 n沟道恒压电路控制p沟道MOS晶体管的驱动，并使电流流过p沟道MOS晶体管，使得通过p沟道MOS晶体管的电流路径恒定或基本恒定。 p沟道恒压电路控制n沟道MOS晶体管的驱动，并使电流流过n沟道MOS晶体管，使得通过n沟道MOS晶体管的电流路径恒定或基本恒定。

公开(公告)号：US5457413A

公开(公告)日：1995-10-10

申请号：US130661

申请日：1993-10-01

申请人： Takashi Oguri

发明人： Takashi Oguri

IPC分类号： H03K17/567 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02

CPC分类号： H03K19/09448 ,  H03K19/013

摘要： A BiMIS circuit has first and second input terminals; first and second output terminals; a first bipolar transistor having a collector receiving a first potential, an emitter connected to the first output terminal, and a base connected to the second output terminal; a second bipolar transistor having a collector connected to the first output terminal and an emitter receiving a reference potential; a first MIS transistor circuit including MIS transistors, connected to the base and the collector of the first bipolar transistor and the first input terminal, and turned on or off depending on a potential of the first input terminal; and a second MIS transistor circuit including MIS transistors, connected to the base of the first bipolar transistor, the second input terminal and the base of the second bipolar transistor, and turned on or off depending on a potential of the second input terminal. The BiMIS circuit includes at least one of: a capacitor having one terminal connected to the first input terminal and the other terminal connected to the base of the second bipolar transistor; a discharging circuit connected to the base of the first bipolar transistor for discharging the base; and a potential setting circuit connected to the base of the second bipolar transistor for setting a potential of the base at a predetermined level.

摘要翻译： BiMIS电路具有第一和第二输入端; 第一和第二输出端子; 具有接收第一电位的集电极的第一双极晶体管，连接到第一输出端子的发射极和连接到第二输出端子的基极; 第二双极晶体管，其具有连接到第一输出端子的集电极和接收参考电位的发射极; 包括MIS晶体管的第一MIS晶体管电路，连接到第一双极晶体管的基极和集电极以及第一输入端，并根据第一输入端的电位导通或截止; 以及第二MIS晶体管电路，其包括连接到第一双极晶体管的基极，第二输入端子和第二双极晶体管的基极的MIS晶体管，并且根据第二输入端子的电位而导通或截止。 BiMIS电路包括以下至少一个：具有连接到第一输入端子的一个端子和连接到第二双极晶体管的基极的另一个端子的电容器; 放电电路，连接到第一双极晶体管的基极，用于对基极进行放电; 以及电位设定电路，连接到第二双极晶体管的基极，用于将基极的电位设定在预定电平。

公开(公告)号：US07443203B2

公开(公告)日：2008-10-28

申请号：US11386813

申请日：2006-03-23

申请人： Takashi Oguri

发明人： Takashi Oguri

IPC分类号： H03K17/16

CPC分类号： H03K19/0005

摘要： An NMOS impedance adjustment circuit has a comparator circuit for comparing with a reference electric potential VREFn a divided voltage potential Vin produced by an NMOS array and an external reference resistance. The NMOS array simulates the impedance of an output buffer circuit on the basis of the comparison result. The comparator circuit has three differential circuits. Three 2-input NAND gates and a single three-input NAND gate take the majority of output values of the differential circuits and output the result from the comparator circuit. A reduction of impedance adjustment precision caused by variability within the chip can thereby be inhibited.

摘要翻译： NMOS阻抗调整电路具有比较电路，用于与由NMOS阵列产生的分压电压Vin和外部参考电阻的参考电位VREFn进行比较。 基于比较结果，NMOS阵列模拟输出缓冲电路的阻抗。 比较器电路具有三个差分电路。 三个2输入NAND门和单个三输入NAND门占据差分电路的大部分输出值，并从比较器电路输出结果。 由此可以抑制由芯片内的变动性引起的阻抗调整精度的降低。

公开(公告)号：US5914546A

公开(公告)日：1999-06-22

申请号：US876531

申请日：1997-06-16

申请人： Katsuyoshi Terakado ,  Shin Onose ,  Takeshi Sakai ,  Yoshiaki Honda ,  Takehiko Watanabe ,  Takashi Oguri ,  Kenji Ishihara

发明人： Katsuyoshi Terakado ,  Shin Onose ,  Takeshi Sakai ,  Yoshiaki Honda ,  Takehiko Watanabe ,  Takashi Oguri ,  Kenji Ishihara

IPC分类号： H02K3/50 ,  H01R4/18 ,  H01R43/058 ,  H02K3/04 ,  H02K15/00 ,  H01R4/10 ,  H02K11/00

CPC分类号： H02K15/0075 ,  H01R4/183 ,  H01R43/058 ,  H02K11/40 ,  H02K15/0056 ,  H02K3/04

摘要： A highly reliable connection structure of a bundle of more than two coil leading-out wires and a wire bundling terminal is provided by contacting and fixing at least a part of a circumferential surface of each of the coil leading-out wires to an inside wall of the wire bundling terminal. Further, a small size motor and an alternator for a vehicle utilize the connection structure.

摘要翻译： 通过使每个线圈导出线的周向表面的至少一部分接触和固定到一个或多个线圈引出线的内壁上，提供一束多于两个的线圈引出线和线捆绑端子的高度可靠的连接结构 电线捆绑终端。 此外，小型电动机和用于车辆的交流发电机利用连接结构。

公开(公告)号：US06194920B1

公开(公告)日：2001-02-27

申请号：US09151773

申请日：1998-09-11

申请人： Takashi Oguri

发明人： Takashi Oguri

IPC分类号： H03F345

CPC分类号： H03F3/303 ,  H03F3/4521 ,  H03F2203/45674

摘要： The invention provides a semiconductor circuit which can accept signals of various levels and operate at a high speed with low power dissipation. The semiconductor circuit includes a PMOS differential circuit having two inputs one of which is connected to a first input terminal and the other of which is connected to a second input terminal, an NMOS differential circuit having two inputs one of which is connected to the first input terminal and the other of which is connected to the second input terminal, and an output circuit operable in response to differential outputs of the PMOS differential circuit and the NMOS differential circuit for preventing, when a current path is formed between an output terminal and a power supply terminal, formation of a current path between a ground terminal and the output terminal, but preventing, when a current path is formed between the output terminal and the ground terminal, formation of a current path between the power supply terminal and the output terminal.

摘要翻译： 本发明提供一种半导体电路，其可以接受各种级别的信号并以低功率耗散的高速度操作。 半导体电路包括具有两个输入的PMOS差分电路，其中一个连接到第一输入端子，另一个连接到第二输入端子，具有两个输入端的NMOS差分电路，其中之一连接到第一输入端 端子，另一个连接到第二输入端子，以及输出电路，其可响应于PMOS差分电路和NMOS差分电路的差分输出而工作，用于在输出端子和电源之间形成电流路径时防止 在接地端子和输出端子之间形成电流路径，但是当在输出端子和接地端子之间形成电流路径时，防止在电源端子和输出端子之间形成电流路径。

公开(公告)号：US6078207A

公开(公告)日：2000-06-20

申请号：US159787

申请日：1998-09-24

申请人： Takashi Oguri

发明人： Takashi Oguri

IPC分类号： H03G11/00 ,  H03F3/45 ,  H03K5/08 ,  H03K19/0175

CPC分类号： H03K5/023 ,  H03F3/45183 ,  H03F2203/45641

摘要： An output amplitude regulating circuit comprises a first MOS differential circuit, with a first MOS transistor connected between an output terminal of the first MOS differential circuit and a power supply. The circuit also includes a second MOS differential circuit having a first input terminal that receives a reference electric potential, and a second MOS transistor that is connected between the power supply and a second input terminal of the second MOS differential circuit, and is connected to a reference electric potential via a third MOS transistor and a current source. In the circuit, output terminals of the first and second MOS transistors are used to regulate an output amplitude from the output terminal of the first MOS differential circuit.

摘要翻译： 输出幅度调节电路包括第一MOS差分电路，其中第一MOS晶体管连接在第一MOS差分电路的输出端和电源之间。 电路还包括具有接收参考电位的第一输入端的第二MOS差分电路和连接在电源和第二MOS差分电路的第二输入端之间的第二MOS晶体管，并连接到 通过第三MOS晶体管和电流源的参考电位。 在该电路中，第一和第二MOS晶体管的输出端用于调节来自第一MOS差分电路的输出端的输出振幅。