公开(公告)号：US20120173850A1

公开(公告)日：2012-07-05

申请号：US13423145

申请日：2012-03-16

申请人： Teppei HIROTSU ,  Yuuichi ABE ,  Takeshi KATAOKA ,  Yasuhiro NAKATSUKA

发明人： Teppei HIROTSU ,  Yuuichi ABE ,  Takeshi KATAOKA ,  Yasuhiro NAKATSUKA

IPC分类号： G06F9/38 ,  G06F13/40 ,  G06F9/312

CPC分类号： G06F9/30054 ,  G06F9/3804 ,  G06F9/382

摘要： A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.

摘要翻译： 能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。 它是配备有CPU，存储器，预取装置等的信息处理装置，其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支 从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址，从而期待分支目的地址。 信息处理装置还包括RTS指令缓冲器，用于存储RTS指令的返回目的地的一系列指令，存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。

公开(公告)号：US07821824B2

公开(公告)日：2010-10-26

申请号：US12258964

申请日：2008-10-27

申请人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

发明人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

IPC分类号： G11C16/04

CPC分类号： G11C16/349 ,  G11C16/06 ,  G11C16/3495

摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.

摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以在保证重写操作次数方面较差; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数。

公开(公告)号：US20080022030A1

公开(公告)日：2008-01-24

申请号：US11779189

申请日：2007-07-17

申请人： Kesami Hagiwara ,  Takeshi Kataoka ,  Hisakazu Sato ,  Shunichi Iwata ,  Yoshikazu Kiyoshige ,  Akihiko Tomita

发明人： Kesami Hagiwara ,  Takeshi Kataoka ,  Hisakazu Sato ,  Shunichi Iwata ,  Yoshikazu Kiyoshige ,  Akihiko Tomita

IPC分类号： G06F13/36

CPC分类号： G06F13/364

摘要： In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit. A high-speed access is made from the second processor to the second local memory via the second local bus. The second local memory is also accessed from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit and from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit.

摘要翻译： 在多处理器中，两个本地存储器之一可以通过两个处理器之一高速访问，并且还可以由另一个处理器访问。 在多处理器中，第一和第二本地存储器经由第一和第二本地总线耦合到第一和第二处理器。 第一和第二总线桥耦合到系统总线和第一和第二本地总线。 第一和第二总线接口单元耦合到系统总线和第一和第二本地存储器。 通过第一本地总线从第一处理器到第一本地存储器进行高速访问。 第一本地存储器还通过第一局部总线，第一总线桥，系统总线以及第二总线接口单元的第一和第三端口以及经由第二本地总线从第二处理器访问第一本地存储器， 第二总线桥，系统总线，以及第一总线接口单元的第二和第三端口。 通过第二本地总线从第二处理器到第二本地存储器进行高速访问。 第二本地存储器还通过第二本地总线，第二总线桥，系统总线以及第一总线接口单元的第二和第三端口以及经由第一本地总线从第一处理器访问第二本地存储器， 第一总线桥，系统总线，以及第二总线接口单元的第一和第三端口。

公开(公告)号：US07290124B2

公开(公告)日：2007-10-30

申请号：US10690643

申请日：2003-10-23

申请人： Yasuo Sugure ,  Tomomi Ishikura ,  Kazuya Hirayanagi ,  Takeshi Kataoka ,  Seiji Takeuchi ,  Hiromichi Yamada ,  Takanaga Yamazaki

发明人： Yasuo Sugure ,  Tomomi Ishikura ,  Kazuya Hirayanagi ,  Takeshi Kataoka ,  Seiji Takeuchi ,  Hiromichi Yamada ,  Takanaga Yamazaki

IPC分类号： G06F9/48

CPC分类号： G06F9/30043 ,  G06F9/3012 ,  G06F9/30123

摘要： The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.

摘要翻译： 本发明防止数据处理器由于多个寄存器组的溢出而不期望的操作停止。 状态寄存器包括用于指示多个寄存器组的溢出的溢出标志。 当数据已被保存到寄存器组的所有存储体的状态中发生中断异常时，允许接受的中断异常使用寄存器组，中央处理单元将寄存器组的数据保存到堆栈区域， 反映溢出标志中的溢出状态。 当溢出标志指示溢出状态时，如果从寄存器组到寄存器组的数据恢复被定向，则中央处理单元将数据从堆栈区恢复到寄存器组。

公开(公告)号：US06351788B1

公开(公告)日：2002-02-26

申请号：US09297310

申请日：1999-06-10

申请人： Takanaga Yamazaki ,  Yasushi Akao ,  Keiichi Kurakazu ,  Masayasu Ohizumi ,  Takeshi Kataoka ,  Tatsuo Nakai ,  Mitsuhiro Miyazaki ,  Yosuke Murayama

发明人： Takanaga Yamazaki ,  Yasushi Akao ,  Keiichi Kurakazu ,  Masayasu Ohizumi ,  Takeshi Kataoka ,  Tatsuo Nakai ,  Mitsuhiro Miyazaki ,  Yosuke Murayama

IPC分类号： G06F1300

CPC分类号： G06F12/0864

摘要： A data processor including a central processing unit and a plurality of direct map cache memories (3, 4) has a plurality of area designating circuits (5, 6) for variably designating location and size of address area in the memory space managed the central processing unit and partially overlaps the address area designated by a plurality of area designating circuits. Thereby, the overlapped area (Eco) has a function as the 2-way set associative cache memory in combination with a plurality of cache memories. For the non-overlapping area, respective cache memory functions as the direct map cache memory. It is previously judged to attain the necessary data processing capability by arranging which processing routine to which address area and then executing such routine with what processing speed. Thereby, when cache object area is assigned to a plurality of cache memory, a plurality of cache memories are combined as a set associative cache for operation to the task which particularly requires high speed operation or to the data. As a result, the system can be optimized by improving the cache hit rate of the necessary area.

摘要翻译： 包括中央处理单元和多个直接地图高速缓存存储器（3,4）的数据处理器具有多个区域指定电路（5,6），用于可变地指定存储器空间中的地址区域的位置和大小来管理中央处理 单元并且部分地重叠由多个区域指定电路指定的地址区域。 因此，重叠区域（Eco）具有与多个高速缓存存储器组合的2路组合关联高速缓冲存储器的功能。 对于非重叠区域，各个高速缓冲存储器用作直接映射高速缓冲存储器。 先前通过安排哪个处理例程到达哪个地址区域，然后以什么处理速度执行这种例程，以前被判定为获得必要的数据处理能力。 因此，当将高速缓存对象区域分配给多个高速缓冲存储器时，将多个高速缓存存储器组合为用于操作的组关联高速缓存，特别需要高速操作或数据。 因此，可以通过提高必要区域的缓存命中率来优化系统。

公开(公告)号：US4515024A

公开(公告)日：1985-05-07

申请号：US379987

申请日：1982-05-19

申请人： Takeshi Kataoka ,  Ryoichi Aoki ,  Hisashi Matsui ,  Hiroshi Matsumoto

发明人： Takeshi Kataoka ,  Ryoichi Aoki ,  Hisashi Matsui ,  Hiroshi Matsumoto

IPC分类号： H03J5/12

CPC分类号： H03J5/12 ,  Y10T74/19502 ,  Y10T74/19828

摘要： Clutch means for changing inductance of a push-button tuner which is compact in size and adapted for use with a tape recorder. The mechanism includes flat slidable cam plates provided with cam portions at the front portions thereof, which are arranged horizontally and slidably through holes of side walls and a push-button assembly slidably arranged in front and rear walls, which is equipped with a channeling plate pivotably mounted thereon, the position of which may be set at a desired angle by means of the operation of a manual shaft when a clutch mechanism is engaged. With the advancement of the push-button assembly, a head thereof touches the cam of the clutch plate arranged in parallel with the slidable cam plate at the front of the push-button assembly whereby the clutch plate is forced to be shifted horizontally against a coil spring the biasing force of which acts on a follower manual shaft supported in an arm hole of the clutch plate which is partially released whereby the clutch mechanism is disengaged by ending the engagement of a rotation means with a gear wheel with which a worm gear mounted on the follower manual shaft is in meshing engagement.

摘要翻译： 离合器用于改变按钮式调谐器的电感，其尺寸紧凑并适用于磁带录音机。 该机构包括在其前部设置有水平且可滑动地穿过侧壁的孔的平滑的可滑动凸轮板和可滑动地布置在前壁和后壁中的按钮组件，该按钮组件可枢转地配备有引导板 当离合器机构接合时，其位置可以通过手动轴的操作而被设置在期望的角度。 随着按钮组件的推进，其头部接触与按钮组件的前部处的可滑动凸轮平行布置的离合器板的凸轮，由此离合器板被迫水平地相对于线圈 弹簧，其作用在支撑在离合器板的臂孔中的随动手动轴上，该随动手动轴被部分地释放，由此通过结束旋转装置与齿轮的啮合，离合器机构脱离，蜗轮安装在该齿轮上 从动手动轴处于啮合状态。

公开(公告)号：US20120179953A1

公开(公告)日：2012-07-12

申请号：US13368461

申请日：2012-02-08

申请人： Yutaka SHINAGAWA ,  Takeshi KATAOKA ,  Eiichi ISHIKAWA ,  Toshihiro TANAKA ,  Kazumasa YANAGISAWA ,  Kazufumi SUZUKAWA

发明人： Yutaka SHINAGAWA ,  Takeshi KATAOKA ,  Eiichi ISHIKAWA ,  Toshihiro TANAKA ,  Kazumasa YANAGISAWA ,  Kazufumi SUZUKAWA

IPC分类号： G11C16/04 ,  G06F11/10 ,  H03M13/05

CPC分类号： G11C16/349 ,  G11C16/06 ,  G11C16/3495

摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.

摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写的非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

公开(公告)号：US08130571B2

公开(公告)日：2012-03-06

申请号：US13162180

申请日：2011-06-16

申请人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

发明人： Yutaka Shinagawa ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

IPC分类号： G11C7/00

CPC分类号： G11C16/349 ,  G11C16/06 ,  G11C16/3495

摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.

摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以不利于保证重写操作的次数; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

公开(公告)号：US20110246860A1

公开(公告)日：2011-10-06

申请号：US13162180

申请日：2011-06-16

申请人： Yutaka SHINAGAWA ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

发明人： Yutaka SHINAGAWA ,  Takeshi Kataoka ,  Eiichi Ishikawa ,  Toshihiro Tanaka ,  Kazumasa Yanagisawa ,  Kazufumi Suzukawa

IPC分类号： H03M13/05 ,  G11C16/04 ,  G06F11/10

CPC分类号： G11C16/349 ,  G11C16/06 ,  G11C16/3495

摘要： A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more.

摘要翻译： 半导体集成电路具有设置在中央处理单元的地址空间中的中央处理单元和可重写非易失性存储区域。 非易失性存储区域具有第一非易失性存储区域和第二非易失性存储器区域，其根据阈值电压的差异来存储信息。 第一非易失性存储区具有用于存储大于第二非易失性存储区的信息的阈值电压的最大变化宽度。 当用于存储信息的阈值电压的最大变化幅度较大时，由于由于存储信息的重写操作而对存储单元的应力变大，所以不利于保证重写操作的次数; 然而，由于读取电流变大，因此可以加快存储器信息的读取速度。 可以优先考虑第一非易失性存储器区域以加快存储器信息的读取速度，并且可以对第二非易失性存储器区域进行优先排列以保证存储器信息的重写操作的次数更多。

公开(公告)号：US07998543B2

公开(公告)日：2011-08-16

申请号：US12281008

申请日：2006-10-17

申请人： Takashi Seki ,  Takeshi Kataoka ,  Hitoshi Mazaki ,  Hirofumi Aizono

发明人： Takashi Seki ,  Takeshi Kataoka ,  Hitoshi Mazaki ,  Hirofumi Aizono

IPC分类号： C09K19/38 ,  C09K19/34 ,  C09K19/20 ,  C09K19/30 ,  C07D305/06 ,  C07D407/10 ,  C07D407/12 ,  C08G65/18

CPC分类号： C07D305/06 ,  C08F220/30 ,  C08G65/18 ,  G02F1/13363 ,  G02F2001/133633 ,  G02F2413/04 ,  G02F2413/06 ,  G02F2413/08 ,  Y10T428/10

摘要： A novel dioxetane compound is provided having a cationically polymerizable oxetane group, which compound is excellent in compatibility with a liquid crystalline compound and a non-liquid crystalline compound. An optical film is also provided with excellent liquid crystal orientation retention properties and mechanical strength, produced by aligning a composition of the dioxetane compound and a cationically polymerizable compound in a liquid crystal orientation and fixing the liquid crystal orientation by polymerization. Further, a liquid crystal display device is provided with the optical film.

摘要翻译： 提供具有阳离子聚合性氧杂环丁烷基的新型二氧杂环丁烷化合物，该化合物与液晶化合物和非液晶化合物的相容性优异。 光学膜还具有优异的液晶取向保持性和机械强度，其通过将液体取向中的二氧杂环丁烷化合物的组成和阳离子聚合性化合物取向并通过聚合固定液晶取向而制备。 此外，液晶显示装置设置有光学膜。