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10 条记录 (耗时 0.029 秒)

    Phase locked loop circuit with adjustable offset characteristic, method for adjustment and apparatus
    5.
    发明授权
    Phase locked loop circuit with adjustable offset characteristic, method for adjustment and apparatus 失效
    具有可调偏移特性的锁相环电路，调节方法和装置

    公开(公告)号：US5677802A

    公开(公告)日：1997-10-14

    申请号：US405895

    申请日：1995-03-17

    申请人： Eisaku Saiki ,  Masashi Mori ,  Shintaro Suzumura ,  Shoichi Miyazawa ,  Terumi Takashi

    发明人： Eisaku Saiki ,  Masashi Mori ,  Shintaro Suzumura ,  Shoichi Miyazawa ,  Terumi Takashi

    IPC分类号： G11B19/02 ,  G11B20/14 ,  G11B20/18 ,  H03L7/06 ,  H03L7/08 ,  H03M1/10 ,  H03M1/12 ,  H04L7/033 ,  G11B5/09 ,  G11B27/36

    CPC分类号： G11B20/10055 ,  G11B19/02 ,  G11B20/1403 ,  G11B20/182

    摘要： A phase locked loop circuit having a voltage controlled oscillator for generating a clock signal with a frequency determined by a voltage control signal supplied to the voltage controlled oscillator, an AD-conversion circuit for sampling a target signal with a timing determined by the clock signal and for converting sampled values into digital data, a phase locked loop control circuit for generating control data with values representing values of the digital data, and a DA-conversion circuit having an adjustable conversion characteristic for converting the control data into an analog signal and for outputting the analog signal to the voltage controlled oscillator as the voltage control signal. The adjustable conversion characteristic of the DA-conversion circuit is adjusted on the basis of an input signal having predetermined playback characteristics and when the phase locked loop circuit is part of a recording and reproducing apparatus, the input signal is a reproduced signal from a signal recorded on a recording medium.

    摘要翻译： 一种锁相环电路，具有用于产生由提供给压控振荡器的电压控制信号确定的频率的时钟信号的压控振荡器，用于由时钟信号确定的定时对目标信号进行采样的AD转换电路，以及 用于将采样值转换为数字数据的锁相环控制电路，用于产生具有表示数字数据值的值的控制数据的锁相环控制电路，以及具有用于将控制数据转换成模拟信号并具有可变输出的可调转换特性的DA转换电路 将压控振荡器的模拟信号作为电压控制信号。 基于具有预定播放特性的输入信号调整DA转换电路的可调转换特性，并且当锁相环电路是记录和再现装置的一部分时，输入信号是从记录的信号的再现信号 在记录介质上。

    Phase-locked loop IC having ECL buffers
    10.
    发明授权
    Phase-locked loop IC having ECL buffers 失效
    具有ECL缓冲器的锁相环IC

    公开(公告)号：US5157354A

    公开(公告)日：1992-10-20

    申请号：US799442

    申请日：1991-11-27

    申请人： Eisaku Saiki ,  Shintaro Suzumura ,  Fukashi Ohi ,  Akira Uragami ,  Tsuyoshi Tateyama

    发明人： Eisaku Saiki ,  Shintaro Suzumura ,  Fukashi Ohi ,  Akira Uragami ,  Tsuyoshi Tateyama

    IPC分类号： G11B20/12 ,  G11B20/14 ,  H03D13/00 ,  H03K19/0175 ,  H03L7/06 ,  H03L7/10 ,  H03L7/107 ,  H03L7/113

    CPC分类号： G11B20/1403 ,  H03D13/004 ,  H03K19/017518 ,  H03L7/107 ,  H03L7/113 ,  G11B20/1258

    摘要： A phase locked loop IC comprising a voltage controlled oscillator which generates a clock signal in accordance with a control voltage, a first ECL input buffer which is an input buffer for a signal to be synchronized, a phase-lock capture circuit for producing a current determinative of the control voltage in accordance with the phase difference and the frequency difference between the signal to be synchronized and the clock signal, and a phase-lock follow-up circuit for producing a current determinative of the control voltage in accordance with the phase difference between the clock signal and the signal to be synchronized; wherein the supply voltage system of the first ECL input buffer is so disposed as to be isolated from any of the supply voltage systems of the voltage-controlled oscillator, the phase-lock capture circuit and the phase lock follow-up circuit, while the ground system of the first ECL input buffer is so disposed as to be insolated from any of the ground systems of the voltage-controlled oscillator, the phase-lock capture circuit and the phase-lock follow-up circuit.

    摘要翻译： 一种锁相环IC，包括根据控制电压产生时钟信号的压控振荡器，作为用于待同步信号的输入缓冲器的第一ECL输入缓冲器，用于产生电流确定性的锁相捕获电路 根据相位差和要同步的信号与时钟信号之间的频率差的控制电压，以及相位锁定跟随电路，用于根据相位差的相位差产生控制电压的电流确定 时钟信号和要同步的信号; 其中第一ECL输入缓冲器的电源电压系统被布置为与压控振荡器，锁相捕获电路和锁相跟随电路的任何一个电压系统隔离，而地 第一ECL输入缓冲器的系统被布置成从压控振荡器，锁相捕获电路和锁相跟随电路的任何地面系统中被绝缘。