公开(公告)号：US06326838B1

公开(公告)日：2001-12-04

申请号：US09389582

申请日：1999-09-03

申请人： Hiroshi Kimura ,  Takushi Nishiya ,  Takatoshi Kato ,  Takashi Nara ,  Seiichi Mita

发明人： Hiroshi Kimura ,  Takushi Nishiya ,  Takatoshi Kato ,  Takashi Nara ,  Seiichi Mita

IPC分类号： H03B100

CPC分类号： H03H11/0422

摘要： A transconductance control circuit is composed of a replica transconductance amplifier and resistance, a reference voltage source, first selectors, a differential amplifier, a voltage-current translate circuit with characteristics equal to the transconductance amplifier which constitutes analog filters. A first switch of the first selectors is connectable for the reference voltage source, and every constant period is made to connect it using clocks at the reference voltage source. A second switch of second selectors is connectable for plural capacitors, and every constant period is made to connect it using clocks at the capacitors.

摘要翻译： 跨导控制电路由复制跨导放大器和电阻，参考电压源，第一选择器，差分放大器，具有等于构成模拟滤波器的跨导放大器的特性的电压 - 电流平移电路组成。 第一选择器的第一开关可连接到参考电压源，并且每个恒定周期都使用参考电压源的时钟进行连接。 第二选择器的第二开关可连接多个电容器，并且每个恒定周期都使用电容器上的时钟来连接。

公开(公告)号：US06373407B1

公开(公告)日：2002-04-16

申请号：US09255733

申请日：1999-02-23

申请人： Takushi Nishiya ,  Tatsuya Hirai ,  Seiichi Mita ,  Takashi Nara ,  Yoichi Uehara ,  Hiroshi Ide ,  Kyoko Tsukano ,  Yoshiju Watanabe

发明人： Takushi Nishiya ,  Tatsuya Hirai ,  Seiichi Mita ,  Takashi Nara ,  Yoichi Uehara ,  Hiroshi Ide ,  Kyoko Tsukano ,  Yoshiju Watanabe

IPC分类号： H03M700

CPC分类号： H03M5/145 ,  G11B20/1426 ,  G11B2020/1446

摘要： The computer system includes a host system, a recording medium, and a digital signal decoder connected to the host system and the recording medium. The digital signal decoder receives M-bit data and generates an N-bit code word from the M-bit data. The number of consecutive bits of 1 in the code word is not larger than a first predetermined number K, and the number of consecutive bits of 0 is not larger than a second predetermined number L. When data is recorded/reproduced by a method such as NRZI (Non-Return to Zero Inverted), or the like, there is a defect in that the number of transitions of data is larger in a code with a high data encoding rate, and the run length of zero is long thereby increasing the data decoding error rate with the recording/reproducing of data. In the digital signal decoder according to the present invention, any code word includes at most 3 consecutive bits of 1, and at most 11 consecutive bits of 0, so that the data decoding error rate can be reduced.

摘要翻译： 计算机系统包括主机系统，记录介质和连接到主机系统和记录介质的数字信号解码器。 数字信号解码器接收M位数据并从M位数据生成N位代码字。 代码字中的连续比特数1不大于第一预定数K，连续比特数0不大于第二预定数L.当通过诸如以下方法记录/再现数据时 NRZI（不归零归零）等，存在数据的转换次数较大的缺点，数据编码速率高的代码，零的行程长，从而增加数据 解码错误率与数据的记录/再现。 在根据本发明的数字信号解码器中，任何代码字包括最多3个连续位1和至多11个连续位0，从而可以减少数据解码错误率。

公开(公告)号：US5940416A

公开(公告)日：1999-08-17

申请号：US881508

申请日：1997-06-24

申请人： Takushi Nishiya ,  Hideyuki Yamakawa ,  Shoichi Miyazawa, deceased ,  Seiichi Mita ,  Yoichi Uehara ,  Takashi Nara ,  Akihiko Hirano

发明人： Takushi Nishiya ,  Hideyuki Yamakawa ,  Shoichi Miyazawa, deceased ,  Seiichi Mita ,  Yoichi Uehara ,  Takashi Nara ,  Akihiko Hirano

IPC分类号： G11B20/18 ,  G11B20/10 ,  H03M13/23 ,  H03M13/41 ,  H04L25/497 ,  H03M13/00

CPC分类号： H03M13/6505 ,  G11B20/10009 ,  H03M13/3961 ,  H03M13/4107

摘要： A calculation concerning the input of a signal is removed from a branch metric calculation processing on a trellis diagram of an extended partial response class, and the calculation of branch metrics and the selection of survivor paths can be carried out by the subtraction of the survivor paths and the comparison of constants.

摘要翻译： 关于信号输入的计算从扩展部分响应类的格状图上的分支度量计算处理中去除，并且分支度量的计算和幸存路径的选择可以通过减去幸存路径来执行 和常数的比较。

公开(公告)号：US20050041316A1

公开(公告)日：2005-02-24

申请号：US10914243

申请日：2004-08-10

申请人： Takatoshi Kato ,  Takushi Nishiya ,  Hideyuki Yamakawa ,  Takashi Nara ,  Nobuaki Nakai ,  Hiroshi Ide ,  Shintaro Suzumura ,  Terumi Takashi

发明人： Takatoshi Kato ,  Takushi Nishiya ,  Hideyuki Yamakawa ,  Takashi Nara ,  Nobuaki Nakai ,  Hiroshi Ide ,  Shintaro Suzumura ,  Terumi Takashi

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  G11B20/20

CPC分类号： G11B20/10009 ,  G11B5/012 ,  G11B5/09 ,  G11B20/1403

摘要： In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

公开(公告)号：US06980385B2

公开(公告)日：2005-12-27

申请号：US10914243

申请日：2004-08-10

申请人： Takatoshi Kato ,  Takushi Nishiya ,  Hideyuki Yamakawa ,  Takashi Nara ,  Nobuaki Nakai ,  Hiroshi Ide ,  Shintaro Suzumura ,  Terumi Takashi

发明人： Takatoshi Kato ,  Takushi Nishiya ,  Hideyuki Yamakawa ,  Takashi Nara ,  Nobuaki Nakai ,  Hiroshi Ide ,  Shintaro Suzumura ,  Terumi Takashi

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/14

CPC分类号： G11B20/10009 ,  G11B5/012 ,  G11B5/09 ,  G11B20/1403

摘要： In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

摘要翻译： 为了产生具有更高精度的采样时钟，同步信号发生电路设置有相位误差检测器，检测基于FDTS算法数字化的读出信号的相位误差和控制振荡频率的VCO 基于由相位误差检测器检测到的相位误差，由VCO产生同步信号。 基于由同步信号发生电路产生的同步信号，ADC对读出的信号进行数字化。 然后，数字化读出信号由检测电路转换成二进制数据。

公开(公告)号：US06791776B2

公开(公告)日：2004-09-14

申请号：US09793924

申请日：2001-02-28

申请人： Takatoshi Kato ,  Takushi Nishiya ,  Hideyuki Yamakawa ,  Takashi Nara ,  Nobuaki Nakai ,  Hiroshi Ide ,  Shintaro Suzumura ,  Terumi Takashi

发明人： Takatoshi Kato ,  Takushi Nishiya ,  Hideyuki Yamakawa ,  Takashi Nara ,  Nobuaki Nakai ,  Hiroshi Ide ,  Shintaro Suzumura ,  Terumi Takashi

IPC分类号： G11B509

CPC分类号： G11B20/10009 ,  G11B5/012 ,  G11B5/09 ,  G11B20/1403

摘要： In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

摘要翻译： 为了产生具有更高精度的采样时钟，同步信号发生电路设置有相位误差检测器，检测基于FDTS算法数字化的读出信号的相位误差和控制振荡频率的VCO 基于由相位误差检测器检测到的相位误差，由VCO产生同步信号。 基于由同步信号发生电路产生的同步信号，ADC对读出的信号进行数字化。 然后，数字化读出信号由检测电路转换成二进制数据。

公开(公告)号：US5774470A

公开(公告)日：1998-06-30

申请号：US524040

申请日：1995-09-06

申请人： Takushi Nishiya ,  Shoichi Miyazawa ,  Kazutoshi Ashikawa ,  Ryushi Shimokawa ,  Seiichi Mita

发明人： Takushi Nishiya ,  Shoichi Miyazawa ,  Kazutoshi Ashikawa ,  Ryushi Shimokawa ,  Seiichi Mita

IPC分类号： G06F11/10 ,  G11B20/10 ,  G11B20/18 ,  H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H03M13/23 ,  H03M13/41 ,  H04B3/04

CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B20/18 ,  H03M13/41 ,  H03M13/6331 ,  H03M13/6505

摘要： A playback signal processing circuit for reducing decode errors and enabling high-density digital magnetic recording and a digital magnetic recording reproducing unit using the playback signal processing circuit are provided. An estimated waveform generation circuit uses the decoding result of a PRML channel to generate an ideal playback signal waveform. A subtractor provides a waveform representing a difference between the waveform and an actual playback signal. There is a high probability that error bits will occur at an interval of two or four bits because of the nature of GCR code and maximum-likelihood decoding; in the error state of each bit, one bit is incremented by one with respect to the correct bit value and the other signal bit is decremented by one. From this fact, an error detection circuit discriminates an error difference waveform pattern and an error discrimination circuit detects an error bit interval, whereby an error correction circuit carries out error bit correction.

摘要翻译： 提供了一种用于减少解码错误并实现高密度数字磁记录的重放信号处理电路和使用重放信号处理电路的数字磁记录再现单元。 估计波形生成电路使用PRML通道的解码结果来产生理想的重放信号波形。 减法器提供表示波形和实际重放信号之间的差异的波形。 由于GCR码的性质和最大似然解码，错误位将以两位或四位的间隔发生的概率很高; 在每个位的错误状态下，一个比特相对于正确的比特值递增1，另一个比特递减1。 根据该事实，误差检测电路鉴别误差波形图案，误差鉴别电路检测误差位间隔，由此误差校正电路进行错误位校正。

公开(公告)号：US20060248427A1

公开(公告)日：2006-11-02

申请号：US11455630

申请日：2006-06-20

申请人： Yukari Katayama ,  Takeshi Maeda ,  Harukazu Miyamoto ,  Takushi Nishiya ,  Takatoshi Kato ,  Shigeki Taira ,  Osamu Kawamae ,  Taku Hoshizawa

发明人： Yukari Katayama ,  Takeshi Maeda ,  Harukazu Miyamoto ,  Takushi Nishiya ,  Takatoshi Kato ,  Shigeki Taira ,  Osamu Kawamae ,  Taku Hoshizawa

IPC分类号： H03M13/00 ,  H04L1/00 ,  G08C25/00 ,  G06F11/00 ,  G06F11/30

CPC分类号： G11B27/329 ,  G11B20/1833 ,  G11B27/034 ,  G11B27/036 ,  G11B2220/216 ,  G11B2220/2562 ,  G11B2220/2575

摘要： A random seed scramble for preventing the deterioration of a medium is applied to the next generation optical disk. A seed is stored to a BIS area. ID or an EDC is checked to hold interchangeability before and after scramble release. When no error is generated in data before the scramble release, it is recognized as an unscrambled disk. In contrast to this, when no error is generated in data after the scramble release, it is recognized as a scrambled disk. An information storing area showing an area to be rewritten by performing the scramble and an area to be rewritten without performing the scramble is arranged.

摘要翻译： 将用于防止介质劣化的随机种子加扰应用于下一代光盘。 种子存储到BIS区域。 检查ID或EDC以在争夺释放之前和之后保持互换性。 在扰频释放前的数据中没有产生错误时，会被识别为未加扰的磁盘。 与此相反，当在扰频释放之后的数据中没有产生错误时，它被识别为加扰的盘。 布置了通过执行扰频而示出要重写的区域的信息存储区域和不进行加扰的要被重写的区域。

公开(公告)号：US5844741A

公开(公告)日：1998-12-01

申请号：US548956

申请日：1995-10-27

申请人： Hideyuki Yamakawa ,  Takushi Nishiya ,  Takashi Nara ,  Terumi Takashi

发明人： Hideyuki Yamakawa ,  Takushi Nishiya ,  Takashi Nara ,  Terumi Takashi

IPC分类号： G11B20/14 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/18 ,  H03M13/23 ,  H04L25/08 ,  H04L25/497 ,  G11B5/035

CPC分类号： G11B20/10175 ,  G11B20/10009 ,  G11B5/012 ,  G11B5/09

摘要： A system for reproducing data recorded on a magnetic recording medium at high density is provided as a simple configuration. Quadripartite reproduction data is output from a Viterbi detection circuit to an adder, which then subtracts the quadripartite reproduction data from a signal before PR4-ML method data determination. An adder is used to perform a (1+D) process for the result. An error signal pattern detection circuit performs maximum likelihood estimation for an PR4-ML method detection error. Further, when a detected determination error matches an actual reproduction data string, a data correction circuit corrects the reproduction data string.

摘要翻译： 作为简单的结构，提供了以高密度再现记录在磁记录介质上的数据的系统。 四维重放数据从维特比检测电路输出到加法器，然后从PR4-ML方法数据确定之前的信号中减去四方再生数据。 使用加法器对结果执行（1 + D）处理。 误差信号图案检测电路对PR4-ML方法检测误差进行最大似然估计。 此外，当检测到的确定错误与实际再现数据串匹配时，数据校正电路校正再现数据串。

公开(公告)号：US4825393A

公开(公告)日：1989-04-25

申请号：US41228

申请日：1987-04-22

申请人： Takushi Nishiya

发明人： Takushi Nishiya

IPC分类号： G01B11/00 ,  G01B11/03 ,  G06T7/00 ,  H04N13/00 ,  G06F15/46

CPC分类号： G01B11/00 ,  G06T7/0075 ,  H04N13/0239 ,  G06T2207/10012 ,  H04N13/0055 ,  H04N13/0221 ,  H04N2013/0081

摘要： Points on a pair of images obtained by imaging an object are finely corresponded in order to precisely measure the three-dimensional position of the object. For this purpose, attractive forces corresponding to features of the images are calculated, and the degree of correspondence between the points on the pair of images is evaluated relying upon the magnitude of the attractive force, in order to determine the corresponding points and to calculate the position of the object relying upon the thus determined corresponding points. Further, an occluded region which contains no corresponding point is detected and is removed, in order to further improve the precision for measuring the position.

摘要翻译： 通过成像对象获得的一对图像上的点被精细对应，以精确地测量对象的三维位置。 为此，计算与图像的特征相对应的吸引力，并且依赖于吸引力的大小来评估该对图像上的点之间的对应程度，以便确定相应的点并计算 依靠这样确定的对应点的对象的位置。 此外，检测并除去不包含对应点的闭塞区域，以进一步提高测量位置的精度。