公开(公告)号：US08237195B2

公开(公告)日：2012-08-07

申请号：US12248874

申请日：2008-10-09

申请人： Tat Ngai ,  Qi Wang ,  Joelle Sharp

发明人： Tat Ngai ,  Qi Wang ,  Joelle Sharp

IPC分类号： H01L29/66

CPC分类号： H01L29/7802 ,  H01L21/6835 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2221/6835 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A field effect transistor device having a strained semiconductor channel region overlying a heterostructure-semiconductor on a metal substrate includes a first semiconductor layer overlying a first metal layer. The first semiconductor layer has a first semiconductor material and a second semiconductor material in a relaxed heterostructure and is heavily doped. A second semiconductor layer overlies the first semiconductor layer and has a first semiconductor material and a second semiconductor material in a relaxed heterostructure. The second semiconductor layer is more lightly doped than the first semiconductor layer. A trench extends into the second semiconductor layer and a channel region has a strained layer of the first semiconductor material adjacent a trench sidewall. The strained channel region provides enhanced carrier mobility and improves performance of the field effect transistor.

摘要翻译： 具有覆盖金属基板上的异质结构半导体的应变半导体沟道区域的场效应晶体管器件包括覆盖第一金属层的第一半导体层。 第一半导体层在松弛异质结构中具有第一半导体材料和第二半导体材料，并且是重掺杂的。 第二半导体层覆盖在第一半导体层上，并且在松弛的异质结构中具有第一半导体材料和第二半导体材料。 第二半导体层比第一半导体层更轻掺杂。 沟槽延伸到第二半导体层中，并且沟道区具有邻近沟槽侧壁的第一半导体材料的应变层。 应变通道区域提供增强的载流子迁移率并且改善场效应晶体管的性能。

公开(公告)号：US20060076046A1

公开(公告)日：2006-04-13

申请号：US11124365

申请日：2005-05-06

申请人： Uttam Ghoshal ,  Tat Ngai ,  Srikanth Samavedam ,  Zhengmao Ye ,  Andrew Miner

发明人： Uttam Ghoshal ,  Tat Ngai ,  Srikanth Samavedam ,  Zhengmao Ye ,  Andrew Miner

IPC分类号： H01L35/30 ,  H01L35/28

CPC分类号： H01L27/16 ,  H01L35/32

摘要： In certain embodiments, a thermoelectric device apparatus includes a plurality of laterally spaced-apart electrodes disposed upon a supporting structure, and at least one complementary pair of thermoelectric elements, each thermoelectric element coupling an electrode to a laterally adjacent electrode. Such a structure reduces the need for solder joints or other structures or mechanisms to attach multiple substrates, components, or assemblies together to form a thermoelectric device.

摘要翻译： 在某些实施例中，热电装置装置包括设置在支撑结构上的多个横向间隔开的电极和至少一对互补的一对热电元件​​，每个热电元件将电极连接到横向相邻的电极。 这种结构减少了对焊点或其它结构或机构的需要，以将多个基板，部件或组件附接在一起以形成热电装置。

公开(公告)号：US20050150539A1

公开(公告)日：2005-07-14

申请号：US11020531

申请日：2004-12-23

申请人： Uttam Ghoshal ,  Srikanth Samavedam ,  Tat Ngai ,  Andrew Miner

发明人： Uttam Ghoshal ,  Srikanth Samavedam ,  Tat Ngai ,  Andrew Miner

IPC分类号： H01L23/38 ,  H01L35/02 ,  H01L35/04 ,  H01L35/12 ,  H01L35/30 ,  H01L35/34 ,  H01L37/00

CPC分类号： H01L23/38 ,  H01L27/16 ,  H01L35/30 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A vertical, monolithic, thin-film thermoelectric device is described. Thermoelectric elements of opposing conductivity types may be coupled electrically in series and thermally in parallel by associated electrodes on a single substrate, reducing the need for mechanisms to attach multiple substrates or components. Phonon transport may be separated from electron transport in a thermoelectric element. A thermoelectric element may have a thickness less than an associated thermalization length. An insulating film between an electrode having a first temperature and an electrode having a second temperature may be a low-thermal conductivity material, a low-k, or ultra-low-k dielectric. Phonon thermal conductivity between a thermoelectric element and an electrode may be reduced without a significant reduction in electron thermal conductivity, as compared to other thermoelectric devices. A phonon conduction impeding material may be included in regions coupling an electrode to an associated thermoelectric element (e.g., a liquid metal).

摘要翻译： 描述了垂直的，整体的薄膜热电装置。 相反导电类型的热电元件可以在单个衬底上由相关联的电极串联电耦合并且热并联，从而减少了附接多个衬底或部件的机构的需要。 声子传输可以与热电元件中的电子传输分离。 热电元件可以具有小于相关联的热化长度的厚度。 具有第一温度的电极和具有第二温度的电极之间的绝缘膜可以是低热导率材料，低k或超低k电介质。 与其他热电装置相比，热电元件和电极之间的声子热导率可以减小而电子热导率显着降低。 声导电阻碍材料可以包括在将电极耦合到相关联的热电元件（例如，液态金属）的区域中。

公开(公告)号：US20050150536A1

公开(公告)日：2005-07-14

申请号：US11020861

申请日：2004-12-23

申请人： Tat Ngai ,  Srikanth Samavedam ,  Uttam Ghoshal

发明人： Tat Ngai ,  Srikanth Samavedam ,  Uttam Ghoshal

IPC分类号： H01L23/38 ,  H01L35/12 ,  H01L35/30 ,  H01L35/34 ,  H01L37/00

CPC分类号： H01L23/38 ,  H01L35/16 ,  H01L35/30 ,  H01L35/34 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A vertical, monolithic, thin-film thermoelectric device is described. Thermoelectric elements of opposing conductivity types may be coupled electrically in series and thermally in parallel by associated electrodes on a single substrate, reducing the need for mechanisms to attach multiple substrates or components. Phonon transport may be separated from electron transport in a thermoelectric element. A thermoelectric element may have a thickness less than an associated thermalization length. An insulating film between an electrode having a first temperature and an electrode having a second temperature may be a low-thermal conductivity material, a low-k, or ultra-low-k dielectric. Phonon thermal conductivity between a thermoelectric element and an electrode may be reduced without a significant reduction in electron thermal conductivity, as compared to other thermoelectric devices. A phonon conduction impeding material may be included in regions coupling an electrode to an associated thermoelectric element (e.g., a liquid metal).

摘要翻译： 描述了垂直的，整体的薄膜热电装置。 相反导电类型的热电元件可以在单个衬底上由相关联的电极串联电耦合并且热并联，从而减少了附接多个衬底或部件的机构的需要。 声子传输可以与热电元件中的电子传输分离。 热电元件可以具有小于相关联的热化长度的厚度。 具有第一温度的电极和具有第二温度的电极之间的绝缘膜可以是低热导率材料，低k或超低k电介质。 与其他热电装置相比，热电元件和电极之间的声子热导率可以减小而电子热导率显着降低。 声导电阻碍材料可以包括在将电极耦合到相关联的热电元件（例如，液态金属）的区域中。

公开(公告)号：US06518106B2

公开(公告)日：2003-02-11

申请号：US09865855

申请日：2001-05-26

申请人： Tat Ngai ,  Bich-Yen Nguyen ,  Vidya S. Kaushik ,  Jamie K. Schaeffer

发明人： Tat Ngai ,  Bich-Yen Nguyen ,  Vidya S. Kaushik ,  Jamie K. Schaeffer

IPC分类号： H01L2100

CPC分类号： H01L21/823842

摘要： A semiconductor device with dual gate electrodes and its method of formation is taught. A first metal/silicon gate stack and a first gate dielectric are formed over a first doped region. The metal/gate stack comprises a metal portion over the first gate dielectric and a first gate portion over the metal portion. A silicon gate and a second gate dielectric are formed over the second doped region. In one embodiment, the first and second gate portions are P+ doped silicon germanium and the metal portion is TaSiN. In another embodiment, the first and second gate portions are N+ doped polysilicon and the metal portion is TaSiN.

公开(公告)号：US20050150535A1

公开(公告)日：2005-07-14

申请号：US11020836

申请日：2004-12-23

申请人： Srikanth Samavedam ,  Uttam Ghoshal ,  Tat Ngai

发明人： Srikanth Samavedam ,  Uttam Ghoshal ,  Tat Ngai

IPC分类号： H01L23/38 ,  H01L35/12 ,  H01L35/30 ,  H01L35/34 ,  H01L37/00

CPC分类号： H01L23/38 ,  H01L35/30 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A vertical, monolithic, thin-film thermoelectric device is described. Thermoelectric elements of opposing conductivity types may be coupled electrically in series and thermally in parallel by associated electrodes on a single substrate, reducing the need for mechanisms to attach multiple substrates or components. Phonon transport may be separated from electron transport in a thermoelectric element. A thermoelectric element may have a thickness less than an associated thermalization length. An insulating film between an electrode having a first temperature and an electrode having a second temperature may be a low-thermal conductivity material, a low-k, or ultra-low-k dielectric. Phonon thermal conductivity between a thermoelectric element and an electrode may be reduced without a significant reduction in electron thermal conductivity, as compared to other thermoelectric devices. A phonon conduction impeding material may be included in regions coupling an electrode to an associated thermoelectric element (e.g., a liquid metal).

摘要翻译： 描述了垂直的，整体的薄膜热电装置。 相反导电类型的热电元件可以在单个衬底上由相关联的电极串联电耦合并且热并联，从而减少了附接多个衬底或部件的机构的需要。 声子传输可以与热电元件中的电子传输分离。 热电元件可以具有小于相关联的热化长度的厚度。 具有第一温度的电极和具有第二温度的电极之间的绝缘膜可以是低热导率材料，低k或超低k电介质。 与其他热电装置相比，热电元件和电极之间的声子热导率可以减小而电子热导率显着降低。 声导电阻碍材料可以包括在将电极耦合到相关联的热电元件（例如，液态金属）的区域中。

公开(公告)号：US20120196414A1

公开(公告)日：2012-08-02

申请号：US13444537

申请日：2012-04-11

申请人： Tat Ngai ,  Qi Wang ,  Joelle Sharp

发明人： Tat Ngai ,  Qi Wang ,  Joelle Sharp

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L21/6835 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2221/6835 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A method for forming a semiconductor device includes forming a graded silicon-germanium (SiGe) layer overlying a silicon substrate, a concentration of germanium increasing with a thickness of the graded silicon germanium layer. A first relaxed SiGe layer is formed over the graded SiGe layer, and a second relaxed SiGe layer overlying the first relaxed SiGe layer. The second relaxed SiGe layer has a lower conductivity than the first relaxed SiGe layer. The method also includes forming a field effect transistor having a trench extending into the second relaxed SiGe layer and a channel region that includes a layer of strained silicon to enable enhanced carrier mobility. A top conductor layer is formed overlying the second relaxed SiGe layer, and then the silicon substrate and the graded SiGe layer are removed. A bottom conductor layer is formed underlying the first relaxed SiGe layer.

摘要翻译： 一种用于形成半导体器件的方法包括形成覆盖硅衬底的梯度硅锗（SiGe）层，锗浓度随着梯度硅锗层的厚度而增加。 在渐变SiGe层上形成第一弛豫SiGe层，并且覆盖第一弛豫SiGe层上的第二弛豫SiGe层。 第二松弛SiGe层具有比第一弛豫SiGe层低的导电性。 该方法还包括形成具有延伸到第二弛豫SiGe层中的沟槽的场效应晶体管和包括应变硅层的沟道区，以实现增强的载流子迁移率。 形成覆盖第二松弛SiGe层的顶导体层，然后去除硅衬底和渐变SiGe层。 底部导体层形成在第一松弛SiGe层下面。

公开(公告)号：US08039877B2

公开(公告)日：2011-10-18

申请号：US12207417

申请日：2008-09-09

申请人： Tat Ngai ,  Qi Wang

发明人： Tat Ngai ,  Qi Wang

IPC分类号： H01L29/04 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/6835 ,  H01L21/76254 ,  H01L29/045 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A method of forming a field effect transistor having a heavily doped p-type (110) semiconductor layer over a metal substrate starts with providing a heavily doped p-type (110) silicon layer, and forming a lightly doped p-type (110) silicon layer on the P heavily doped-type (110) silicon layer. The method also includes forming a p-channel MOSFET which has a channel region along a (110) crystalline plane in the lightly doped p-type (110) silicon layer to allow a current conduction in a direction. The p-channel MOSFET also includes a gate dielectric layer having a high dielectric constant material lining the (110) crystalline plane. The method further includes forming a top conductor layer overlying the lightly doped p-type (110) silicon layer and a bottom conductor layer underlying the heavily doped p-type (110) silicon layer. A current conduction from the top conductor layer to the bottom conductor layer is characterized by a hole mobility along a crystalline orientation and on a (110) crystalline plane.

摘要翻译： 在金属衬底上形成具有重掺杂p型（110）半导体层的场效应晶体管的方法开始于提供重掺杂的p型（110）硅层，并形成轻掺杂的p型（110） 在P重掺杂型（110）硅层上的硅层。 该方法还包括形成p沟道MOSFET，该p沟道MOSFET在轻掺杂p型（110）硅层中具有沿着（110）晶面的沟道区，以允许<110>方向上的电流传导。 p沟道MOSFET还包括具有衬在（110）晶体平面上的高介电常数材料的栅介质层。 该方法还包括形成覆盖轻掺杂p型（110）硅层的顶部导体层和位于重掺杂p型（110）硅层下面的底部导体层。 从顶部导体层到底部导体层的电流传导的特征在于沿<110>晶体取向的空穴迁移率和（110）晶体平面上的空穴迁移率。

公开(公告)号：US20100078682A1

公开(公告)日：2010-04-01

申请号：US12248874

申请日：2008-10-09

申请人： Tat Ngai ,  Qi Wang ,  Joelle Sharp

发明人： Tat Ngai ,  Qi Wang ,  Joelle Sharp

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/6835 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2221/6835 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A field effect transistor device having a strained semiconductor channel region overlying a heterostructure-semiconductor on a metal substrate includes a first semiconductor layer overlying a first metal layer. The first semiconductor layer has a first semiconductor material and a second semiconductor material in a relaxed heterostructure and is heavily doped. A second semiconductor layer overlies the first semiconductor layer and has a first semiconductor material and a second semiconductor material in a relaxed heterostructure. The second semiconductor layer is more lightly doped than the first semiconductor layer. A trench extends into the second semiconductor layer and a channel region has a strained layer of the first semiconductor material adjacent a trench sidewall. The strained channel region provides enhanced carrier mobility and improves performance of the field effect transistor.

摘要翻译： 具有覆盖金属基板上的异质结构半导体的应变半导体沟道区域的场效应晶体管器件包括覆盖第一金属层的第一半导体层。 第一半导体层在松弛异质结构中具有第一半导体材料和第二半导体材料，并且是重掺杂的。 第二半导体层覆盖在第一半导体层上，并且在松弛的异质结构中具有第一半导体材料和第二半导体材料。 第二半导体层比第一半导体层更轻掺杂。 沟槽延伸到第二半导体层中，并且沟道区具有邻近沟槽侧壁的第一半导体材料的应变层。 应变通道区域提供增强的载流子迁移率并且改善场效应晶体管的性能。

公开(公告)号：US20100059797A1

公开(公告)日：2010-03-11

申请号：US12207417

申请日：2008-09-09

申请人： TAT NGAI ,  QI WANG

发明人： TAT NGAI ,  QI WANG

IPC分类号： H01L29/04 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/6835 ,  H01L21/76254 ,  H01L29/045 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A method of forming a field effect transistor having a heavily doped p-type (110) semiconductor layer over a metal substrate starts with providing a heavily doped p-type (110) silicon layer, and forming a lightly doped p-type (110) silicon layer on the P heavily doped-type (110) silicon layer. The method also includes forming a p-channel MOSFET which has a channel region along a (110) crystalline plane in the lightly doped p-type (110) silicon layer to allow a current conduction in a direction. The p-channel MOSFET also includes a gate dielectric layer having a high dielectric constant material lining the (110) crystalline plane. The method further includes forming a top conductor layer overlying the lightly doped p-type (110) silicon layer and a bottom conductor layer underlying the heavily doped p-type (110) silicon layer. A current conduction from the top conductor layer to the bottom conductor layer is characterized by a hole mobility along a crystalline orientation and on a (110) crystalline plane.

摘要翻译： 在金属衬底上形成具有重掺杂p型（110）半导体层的场效应晶体管的方法开始于提供重掺杂的p型（110）硅层，并形成轻掺杂的p型（110） 在P重掺杂型（110）硅层上的硅层。 该方法还包括形成p沟道MOSFET，该p沟道MOSFET在轻掺杂p型（110）硅层中具有沿着（110）晶面的沟道区，以允许<110>方向上的电流传导。 p沟道MOSFET还包括具有衬在（110）晶体平面上的高介电常数材料的栅介质层。 该方法还包括形成覆盖轻掺杂p型（110）硅层的顶部导体层和位于重掺杂p型（110）硅层下面的底部导体层。 从顶部导体层到底部导体层的电流传导的特征在于沿<110>晶体取向的空穴迁移率和（110）晶体平面上的空穴迁移率。