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公开(公告)号：US06985010B2
公开(公告)日：2006-01-10
申请号：US10753056
申请日：2004-01-06
IPC分类号： H03K19/003
摘要： Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.
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2.发明授权公开(公告)号：US06940302B1
公开(公告)日：2005-09-06
申请号：US10338921
申请日：2003-01-07
IPC分类号： H03K19/0185 , H03K19/177 , H04L25/02 , H03K17/16
CPC分类号： H03K19/17744 , H03K19/018585 , H03K19/1778 , H04L25/0272 , H04L25/0286
摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.
摘要翻译： 提供了具有差分I / O电路的可编程逻辑器件集成电路。 差分I / O电路可以包括用于在输出线对之间提供差分数字输出数据信号的输出驱动器。 用户可以对I / O电路进行编程，以适应不同的高速差分I / O信号标准。 用户还可以对I / O电路进行编程，以向输出数据信号提供期望量的预加重。
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3.发明授权公开(公告)号：US07307446B1
公开(公告)日：2007-12-11
申请号：US11510514
申请日：2006-08-24
IPC分类号： H03K17/16
CPC分类号： H03K19/018585 , H03K5/06 , H03K5/13 , H03K5/151 , H03K2005/00032 , H03K2005/00065
摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.
摘要翻译： 提供了具有差分I / O电路的可编程逻辑器件集成电路。 差分I / O电路可以包括用于在输出线对之间提供差分数字输出数据信号的输出驱动器。 用户可以对I / O电路进行编程，以适应不同的高速差分I / O信号标准。 用户还可以对I / O电路进行编程，以向输出数据信号提供期望量的预加重。
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公开(公告)号：US06737885B1
公开(公告)日：2004-05-18
申请号：US10327284
申请日：2002-12-20
IPC分类号： H03K19003
摘要： Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.
摘要翻译： 提供集成电路装置，其包括指示电源是否达到功能电压电平的功率检测电路。 功率检测电路包括耦合到电源的锁存器，其可以检测所有电源是否已经达到功能电压电平，逻辑电路以提供适当的输出信号，以及向电力检测电路提供电流的阱偏置电路。 良好的偏置电路提供来自第一电源的电流以达到功能电压电平，使得可以从功率检测电路提供指示，而不需要所有电源的功能电压电平。 来自功率检测电路的输出可以与控制信号组合，用于各种应用。 应用包括将集成电路器件置于复位状态，直到电源达到功能电压电平。
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公开(公告)号：US06549032B1
公开(公告)日：2003-04-15
申请号：US09935186
申请日：2001-08-22
IPC分类号： H03K19003
摘要： Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.
摘要翻译： 提供集成电路装置，其包括指示电源是否达到功能电压电平的功率检测电路。 功率检测电路包括耦合到电源的锁存器，其可以检测所有电源是否已经达到功能电压电平，逻辑电路以提供适当的输出信号，以及向电力检测电路提供电流的阱偏置电路。 良好的偏置电路提供来自第一电源的电流以达到功能电压电平，使得可以从功率检测电路提供指示，而不需要所有电源的功能电压电平。 来自功率检测电路的输出可以与控制信号组合，用于各种应用。 应用包括将集成电路器件置于复位状态，直到电源达到功能电压电平。
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公开(公告)号：US08537954B2
公开(公告)日：2013-09-17
申请号：US12688617
申请日：2010-01-15
IPC分类号： H03D3/24
CPC分类号： H03L7/0998 , H03L7/081 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/0025 , H04L7/0083 , H04L7/033
摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.
摘要翻译： 所公开的发明是使用容纳灵活范围操作频率F和连续相同数字要求CID的多模式时钟数据恢复（CDR）电路产生恢复的时钟信号的技术。 在第一操作模式中，受控振荡器产生恢复的时钟信号，并且在第二操作模式中，相位内插器产生恢复的时钟信号。 （CID / F）小于阈值时间值，如果（CID / F）大于阈值时间值，则多模式CDR电路以第一模式工作。
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公开(公告)号：US07154324B1
公开(公告)日：2006-12-26
申请号：US10935867
申请日：2004-09-07
IPC分类号： H03H3/26
CPC分类号： H03K5/133 , H03K2005/00039 , H03K2005/00058 , H03K2005/00143
摘要： Delay chain circuitry is provided. The delay chain circuitry has a number of delay chain inverters. Each delay chain inverter is connected in series with a load resistor and has an associated capacitor between its input and ground. The electrodes of each capacitor may be formed from metal separated by non-gate-oxide dielectric to maintain accurate capacitor tolerances. A stable current source such as a bandgap reference current source may apply a current to a sensing resistor. The resulting bias voltage is indicative of changes in resistance due to changes in operating temperature. A temperature compensation circuit may use the bias voltage to produce temperature-compensation control signals. The temperature-compensation control signals are applied to the delay chain inverters to adjust their resistances and compensate for temperature-induced changes in the resistances of the load resistors. This ensures that the delay of the delay chain is independent of operating temperature.
摘要翻译： 提供延迟链电路。 延迟链电路具有多个延迟链逆变器。 每个延迟链逆变器与负载电阻串联连接，并在其输入和地之间具有相关的电容器。 每个电容器的电极可以由由非栅极 - 氧化物电介质分离的金属形成，以保持精确的电容器公差。 诸如带隙参考电流源的稳定电流源可以向感测电阻器施加电流。 所产生的偏置电压表示由于工作温度变化引起的电阻变化。 温度补偿电路可以使用偏置电压来产生温度补偿控制信号。 温度补偿控制信号被施加到延迟链逆变器以调整其电阻并补偿负载电阻器的电阻的温度引起的变化。 这确保延迟链的延迟与工作温度无关。
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公开(公告)号：US07135887B1
公开(公告)日：2006-11-14
申请号：US11013213
申请日：2004-12-14
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/177
摘要： Programmable logic device integrated circuitry having I/O circuitry portions having different maximum speed capabilities and different amounts of programmability for supporting various I/O signaling standards is provided. High-speed I/O circuitry and low-speed I/O circuitry may be provided. The high-speed I/O circuitry may have differential I/O drivers and may not be programmable. Relatively few I/O lines may be connected to the high-speed I/O circuitry. The low-speed I/O circuitry may be programmable so that a user may configure the low-speed I/O circuitry to support different I/O signaling standards. Intermediate-speed I/O circuitry may be provided that is more flexible than the high-speed circuitry and operates at higher maximum I/O data rates than the low-speed I/O circuitry. Transmitter circuitry (output driver circuitry) in the I/O circuitry may be provided with the ability to handle a greater number of different I/O signaling standards than receiver circuitry (input driver circuitry) in the I/O circuitry.
摘要翻译： 提供了具有不同最大速度能力的I / O电路部分和用于支持各种I / O信令标准的不同数量的可编程性的可编程逻辑器件集成电路。 可以提供高速I / O电路和低速I / O电路。 高速I / O电路可能具有差分I / O驱动器，可能无法编程。 相对较少的I / O线可能连接到高速I / O电路。 低速I / O电路可以是可编程的，使得用户可以配置低速I / O电路以支持不同的I / O信令标准。 可以提供比高速电路更灵活的中速I / O电路，并且以比低速I / O电路更高的最大I / O数据速率工作。 I / O电路中的发射机电路（输出驱动器电路）可以具有处理比I / O电路中的接收机电路（输入驱动器电路）更多数量的不同I / O信令标准的能力。
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公开(公告)号：US20100119024A1
公开(公告)日：2010-05-13
申请号：US12688617
申请日：2010-01-15
IPC分类号： H04L7/00
CPC分类号： H03L7/0998 , H03L7/081 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/0025 , H04L7/0083 , H04L7/033
摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.
摘要翻译： 所公开的发明是使用容纳灵活范围操作频率F和连续相同数字要求CID的多模式时钟数据恢复（CDR）电路产生恢复的时钟信号的技术。 在第一操作模式中，受控振荡器产生恢复的时钟信号，并且在第二操作模式中，相位内插器产生恢复的时钟信号。 （CID / F）小于阈值时间值，如果（CID / F）大于阈值时间值，则多模式CDR电路以第一模式工作。
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公开(公告)号：US06831480B1
公开(公告)日：2004-12-14
申请号：US10338920
申请日：2003-01-07
IPC分类号： G06F738
CPC分类号： H03K19/177
摘要： Programmable logic device integrated circuitry having I/O circuitry portions having different maximum speed capabilities and different amounts of programmability for supporting various I/O signaling standards is provided. High-speed I/O circuitry and low-speed I/O circuitry may be provided. The high-speed I/O circuitry may have differential I/O drivers and may not be programmable. Relatively few I/O lines may be connected to the high-speed I/O circuitry. The low-speed I/O circuitry may be programmable so that a user may configure the low-speed I/O circuitry to support different I/O signaling standards. Intermediate-speed I/O circuitry may be provided that is more flexible than the high-speed circuitry and operates at higher maximum I/O data rates than the low-speed I/O circuitry. Transmitter circuitry (output driver circuitry) in the I/O circuitry may be provided with the ability to handle a greater number of different I/O signaling standards than receiver circuitry (input driver circuitry) in the I/O circuitry.
摘要翻译： 提供了具有不同最大速度能力的I / O电路部分和用于支持各种I / O信令标准的不同数量的可编程性的可编程逻辑器件集成电路。 可以提供高速I / O电路和低速I / O电路。 高速I / O电路可能具有差分I / O驱动器，可能无法编程。 相对较少的I / O线可能连接到高速I / O电路。 低速I / O电路可以是可编程的，使得用户可以配置低速I / O电路以支持不同的I / O信令标准。 可以提供比高速电路更灵活的中速I / O电路，并且以比低速I / O电路更高的最大I / O数据速率工作。 I / O电路中的发射机电路（输出驱动器电路）可以具有处理比I / O电路中的接收机电路（输入驱动器电路）更多数量的不同I / O信令标准的能力。
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