-
公开(公告)号：US6081226A
公开(公告)日：2000-06-27
申请号：US113210
申请日：1998-07-10
CPC分类号： G01S13/106 , G01S7/282 , G01S7/288 , G01S2013/0272
摘要： A radar exciter including a direct digital synthesis (DDS) wideband waveform generator which performs the frequency synthesis function heretofore performed by a direct analog synthesizer. This is achieved by deriving the DDS frequencies, the exciter RF frequencies, the radar synchronizer clock frequency and receiver analog/digital (A/D) converter clock frequency from a common signal source generating a master frequency. The present invention eliminates the direct analog synthesizer and relies solely on the digital generation of waveforms by a DDS wideband waveform generator which performs a discrete sampling process so as to provide coherent frequency and timing relationships.
摘要翻译： 包括直接数字合成（DDS）宽带波形发生器的雷达激励器，其执行由直接模拟合成器执行的频率合成功能。 这是通过从产生主频率的公共信号源导出DDS频率，激励器RF频率，雷达同步器时钟频率和接收器模拟/数字（A / D）转换器时钟频率来实现的。 本发明消除了直接模拟合成器，并且仅依赖于执行离散采样处理以提供相干频率和时序关系的DDS宽带波形发生器的数字生成波形。
-
公开(公告)号：US4521896A
公开(公告)日：1985-06-04
申请号：US378461
申请日：1982-05-14
CPC分类号： G11C27/04
摘要： A dual transport channel charge coupled device for coherently processing two analog signals in a bandwidth compression mode of operation, especially for use in a high resolution coherent radar system, is disclosed. An input charge injection stage is included for each transport channel. The input stages are dependently operative to simultaneously inject charge quantities correspondingly representative of concurrent samplings of the two analog signals being processed into their corresponding associated transport channels. Each transport channel comprises N multi-phase controlled stages in an in-line arrangement with the stages of one transport channel respectively corresponding to the stages of the other, the stages being operative to transport the simultaneously injected charge quantities concurrently along their corresponding channels. Further included are two output buffer amplifier stages respectively corresponding to the transport channels, which are operative to convert the charge quantities transported simultaneously from the dual channels into a coherent time series of analog signals representative thereof. More specifically, the dual input charge injection stages are dependently operative with a common sampling gate to simultaneously input charge quantities into their correspondingly associated transport channels at sampling rates up to at least 60 megahertz. Accordingly, at a subsequent time, the stored charge quantities may be transferred from the dual channel charge coupled device at a much slower rate, say on the order of 2 megahertz, for example.
摘要翻译： 公开了一种双传输信道电荷耦合器件，用于在带宽压缩工作模式下相干地处理两个模拟信号，特别是用于高分辨率相干雷达系统中。 每个传输信道包括输入电荷注入级。 输入级依次操作以同时注入相应代表被处理成相应的相关传输信道的两个模拟信号的并行取样的电荷量。 每个传输信道包括与分别对应于另一个传输信道的一个传输信道的级的在线布置的N个多相控制级，该级可操作以沿其相应的信道同时传送同时注入的电荷量。 另外包括分别对应于传输信道的两个输出缓冲放大器级，其可操作以将从双通道同时传输的电荷量转换成代表其的相干时间序列的模拟信号。 更具体地说，双输入电荷注入阶段依赖于公共采样门的操作，以便以高达至少60兆赫兹的采样速率将电荷量同时输入到相应的相关联的传输信道中。 因此，在随后的时间，所存储的电荷量可以例如以比较慢的速率从双通道电荷耦合器件传送，例如大约2兆赫。
-
公开(公告)号：US4267513A
公开(公告)日：1981-05-12
申请号：US73479
申请日：1979-09-07
CPC分类号： H03K3/2821 , G01S13/282
摘要： An impulse generator apparatus for a high resolution Chirp radar utilizing a fast settling time VHF oscillator in combination with a digital counter and a low phase distortion output filter to provide a sharp gated sinusoid impulse waveform to excite the receiver dispersive delay line.
摘要翻译： 一种用于高分辨率啁啾雷达的脉冲发生器装置，其利用快速建立时间VHF振荡器与数字计数器和低相位失真输出滤波器组合，以提供尖锐的门控正弦波脉冲波形来激励接收器色散延迟线。
-
公开(公告)号：US5369411A
公开(公告)日：1994-11-29
申请号：US69499
申请日：1993-06-01
申请人： Thomas K. Lisle, Jr.
发明人： Thomas K. Lisle, Jr.
CPC分类号： G01S7/4021 , G01S2007/2886
摘要： A method of correcting phase and amplitude imbalances of I and Q components using digital correction coefficients. The amplitude Gc and phase coefficient Pc obtained solely in the time domain from a pilot signal. The I and Q components of the pilot signal are sampled over at least one integer cycle after which the number of samples taken during an integer number of cycles is determined for the samples of the component with the steepest slope. The sums of self and cross products are used to calculate the coefficients.
摘要翻译： 使用数字校正系数校正I和Q分量的相位和幅度不平衡的方法。 仅在导频信号的时域中获得的振幅Gc和相位系数Pc。 导频信号的I和Q分量在至少一个整数周期内进行采样，之后，对于具有最陡斜率的分量的采样，确定在整数周期期间采集的采样数。 自我和交叉积的总和用于计算系数。
-
公开(公告)号：US4642644A
公开(公告)日：1987-02-10
申请号：US618287
申请日：1984-06-07
IPC分类号： G01S7/36
摘要： A method for distinguishing between multiple noise jammer sources having different noise modulation bandwidths. Noise signals are detected by a receiver having a bandwidth substantially the same as the bandwidth of the jammer noise source. The dwell time of the noise pulses formed by the receiver provides a means for determining the noise modulation bandwidth of a noise jammer source.
摘要翻译： 一种用于区分具有不同噪声调制带宽的多个噪声干扰源的方法。 噪声信号由具有与干扰源噪声源的带宽基本相同的带宽的接收机检测。 由接收器形成的噪声脉冲的驻留时间提供了一种用于确定噪声干扰源的噪声调制带宽的装置。
-
6.发明授权Automatic bias adjustment circuit for a successive ranged analog/digital converter 失效用于连续范围的模拟/数字转换器的自动偏置调整电路
公开(公告)号：US4193066A
公开(公告)日：1980-03-11
申请号：US898047
申请日：1978-04-20
CPC分类号： H03M1/1014
摘要： An automatic bias adjustment circuit for a successive ranged analog/digital converter (SRADC) that eliminates the need for manual bias adjustments and calibration inputs. The bias correction circuit comprehends dual flip flops that are triggered by selected comparators of the SRADC n bit parallel analog/digital converter. The flip flop output signals control up/down counters whose output bits drive digital/analog converter. The digital/analog converted signals are introduced back into the SRADC analog chain to zero bias errors in a particular sub-range. A disabling circuit prevents operation of the bias adjustment circuits for the first sub-range.
摘要翻译： 用于连续范围的模拟/数字转换器（SRADC）的自动偏置调整电路，无需手动偏置调整和校准输入。 偏置校正电路包括由SRADC n位并行模拟/数字转换器的选定比较器触发的双触发器。 触发器输出信号控制上/下计数器，其输出位驱动数模转换器。 数字/模拟转换信号被引回到SRADC模拟链中以将特定子范围内的零偏置误差归零。 禁用电路防止第一子范围的偏置调整电路的操作。
-
公开(公告)号：US3956746A
公开(公告)日：1976-05-11
申请号：US539133
申请日：1975-01-07
摘要： An analog-to-digital conversion circuit of the type employing a feedback-type, successive subranging mode of operation is provided. The circuit achieves bipolar input capability using an internal subranging A/C converter which has only a unipolar capability using a single level, unipolar, add-only binary summer to combine successive subranges. The foregoing have been achieved by means of a novel combination of relatively simple circuit elements which have fast settling times.
摘要翻译： 提供了一种采用反馈型连续的次级运行模式的模数转换电路。 该电路使用内部子系统A / C转换器实现双极性输入能力，该转换器仅使用单级，单极性，加法二进制夏季才能组合连续的子范围。 上述已经通过具有快速建立时间的相对简单的电路元件的新颖组合来实现。
-
8.发明授权A/D converter system with error correction and calibration apparatus and method 失效具有误差校正和校准装置和方法的A / D转换器系统
公开(公告)号：US4903024A
公开(公告)日：1990-02-20
申请号：US111765
申请日：1987-10-23
CPC分类号： G01R35/005 , H03M1/1085 , H03M1/109 , H03M1/12
摘要： An analog to digital converter system is disclosed as comprising a conversion circuit operative for developing a digital output corresponding to the magnitude of an input analog signal, a calibration port arranged for receiving digital calibration data from an external source, adjustable calibration circuitry associated with the conversion circuit, and an adjustment mechanism for adjusting the calibration circuitry in response to data applied to the calibration port.
摘要翻译： 公开了一种模数转换器系统，其包括：转换电路，用于开发对应于输入模拟信号幅度的数字输出;布置成用于从外部源接收数字校准数据的校准端口，与转换相关联的可调节校准电路 电路，以及用于响应于应用于校准端口的数据来调整校准电路的调整机构。
-
公开(公告)号：US4194186A
公开(公告)日：1980-03-18
申请号：US898067
申请日：1978-04-20
CPC分类号： H03M1/1014
摘要： Noise induced hunting is eliminated in successive ranged digital/analog converter bias correction circuits by means of a digital hysteresis circuit. The digital hysteresis circuit comprehends a first up/down counter that counts to its extremums from a pre-set intermediate state in response to enable and up/down input signals. For each extremum count an enable output pulse and a reset pulse is generated at the counter output. The enable output pulses are counted by a second up/down counter the output of which drives a digital/analog converter. Each reset pulse resets the first up/down counter to its pre-set state.
摘要翻译： 在数字/模拟转换器偏置校正电路中通过数字滞后电路消除了噪声诱发的振荡。 数字滞后电路包括响应于使能和上/下输入信号从预置的中间状态计数到其极值的第一上/下计数器。 对于每个极值计数，在计数器输出端产生使能输出脉冲和复位脉冲。 使能输出脉冲由第二个上/下计数器计数，其输出驱动数模转换器。 每个复位脉冲将第一个上/下计数器复位到其预置状态。
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.014 秒)