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公开(公告)号：US20060128041A1
公开(公告)日：2006-06-15
申请号：US11339687
申请日：2006-01-26
IPC分类号： H01L21/66
CPC分类号： G03F9/7088 , G03F7/70633 , G03F7/70658 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.
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公开(公告)号：US07015050B2
公开(公告)日：2006-03-21
申请号：US10718612
申请日：2003-11-24
IPC分类号： H01L21/00
CPC分类号： G03F9/7088 , G03F7/70633 , G03F7/70658 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.
摘要翻译： 提供了用于确定在集成电路制造工艺中发生的不对准的测试结构和测试方法。 测试结构包括具有第一测试结构和第二测试结构的第一导电层，其上的电介质层和介电层上的第二导电层。 第二导电层包括在第一方向和第二方向上分别与第一测试结构和第二测试结构的一部分重叠的第三测试结构和第四测试结构。 第一方向与第二方向相反。 该方法包括测量第一和第二导电层之间的电特性以计算由不对准引起的偏移量的步骤。
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3.发明授权Method and device for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal 有权用于检测DRAM装置中位线接触和有源区的对准是否正常的方法和装置公开(公告)号：US06844207B2
公开(公告)日：2005-01-18
申请号：US10452179
申请日：2003-06-02
CPC分类号： G11C29/50008 , G11C11/401 , G11C29/02 , G11C29/025
摘要： Method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, and a test device thereof. In the present invention a plurality of memory cells are formed in the memory area and at least one test device is formed in the scribe line region simultaneously. A first resistance and a second resistance are detected by the test device. Normal alignment of the bit line and the bar-type active area of the test device is determined according to the first resistance and the second resistance. Finally, whether the alignment of the bit line contacts and the active areas in memory areas is normal is determined according to whether the alignment of the bit line contact and bar-type active area of the test device is normal.
摘要翻译： 用于检测DRAM装置中位线接触和有源区的对准是否正常的方法及其测试装置。 在本发明中，在存储区域中形成多个存储单元，同时在划线区域中形成至少一个测试装置。 第一电阻和第二电阻由测试装置检测。 根据第一电阻和第二电阻确定测试装置的位线和条形有源区域的正常对准。 最后，根据测试装置的位线接触和条形有源区域的对准是否正常来确定位线触点的对齐和存储区域中的有效区域是否正常。
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4.发明授权Test key and method for validating the position of a word line overlaying a trench capacitor in DRAMS 有权用于验证DRAMS中覆盖沟槽电容的字线位置的测试键和方法公开(公告)号：US06825053B2
公开(公告)日：2004-11-30
申请号：US10601386
申请日：2003-06-23
申请人： Tie Jiang Wu , Chien-Chang Huang , Yu-Wei Ting , Bo Ching Jiang
发明人： Tie Jiang Wu , Chien-Chang Huang , Yu-Wei Ting , Bo Ching Jiang
IPC分类号： H01L2166
CPC分类号： H01L27/10861 , G11C8/14 , H01L22/34 , H01L27/0207 , H01L27/1087 , H01L27/10891
摘要： A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.
摘要翻译： 用于验证覆盖DRAM的深沟槽电容器的字线结构的位置的测试键。 测试键被沉积在晶片的划线区域中。 深沟槽电容器沉积在划线区域并具有掩埋板。 在划线中沉积矩形字线并覆盖深沟槽电容器的一部分，并且在深沟槽上方沉积两条经过的字线。 第一掺杂区域和第二掺杂区域分别沉积在矩形字线和第一通过字线之间以及矩形字线和第二通过字线之间。 第一插头，第二插头和第三插头分别耦合到第一掺杂区域，第二掺杂区域和掩埋板。
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5.发明授权Device and method for detecting alignment of deep trench capacitors and word lines in DRAM devices 有权用于检测DRAM器件中深沟槽电容器和字线的对准的装置和方法公开(公告)号：US06801462B2
公开(公告)日：2004-10-05
申请号：US10612857
申请日：2003-07-03
申请人： Ming Cheng Chang , Jeng-Ping Lin , Tie Jiang Wu
发明人： Ming Cheng Chang , Jeng-Ping Lin , Tie Jiang Wu
IPC分类号： G11C700
CPC分类号： H01L27/10894 , G11C11/401 , G11C29/02 , G11C29/025 , H01L22/34 , H01L27/10861 , H01L27/10873 , H01L27/10891 , H01L27/10897
摘要： A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices. In the test device, parallel first and second bar-type deep trenches capacitors are disposed in the scribe line region. The first and second bar-type deep trenches capacitors extend to the first and second pairs of memory cells in the memory region adjacent to the first active area respectively. The first and second bar-type deep trenches capacitors are electrically coupled to bit line contacts of the first and second pairs of memory cells respectively. First and second transistors have sources coupled to the first and second bar-type deep trenches capacitors respectively. A first bit line contact is electrically coupled to drains of the first and second transistors.
摘要翻译： 用于检测DRAM器件中的字线和深沟槽电容器的对准的测试装置和方法。 在测试装置中，平行的第一和第二条形深沟槽电容器设置在划线区域中。 第一和第二条形深沟槽电容器分别延伸到与第一有效区域相邻的存储器区域中的第一和第二对存储单元。 第一和第二条形深沟槽电容器分别电耦合到第一和第二对存储器单元的位线触点。 第一和第二晶体管分别具有耦合到第一和第二条形深沟槽电容器的源极。 第一位线接触件电耦合到第一和第二晶体管的漏极。
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公开(公告)号：US06788598B2
公开(公告)日：2004-09-07
申请号：US10448661
申请日：2003-05-30
申请人： Ming-Cheng Chang , Tie-Jiang Wu , Jeng-Ping Lin , Tse-Main Kuo , Hsu-Cheng Fan
发明人： Ming-Cheng Chang , Tie-Jiang Wu , Jeng-Ping Lin , Tse-Main Kuo , Hsu-Cheng Fan
IPC分类号： G11C700
CPC分类号： H01L27/10861 , G11C11/401 , G11C29/50 , G11C2029/5002 , G11C2029/5004 , H01L22/34 , H01L27/0207 , H01L27/10891 , H01L29/66181
摘要： A test key disposed on a scribe line of a wafer. The test key includes: two active areas disposed on the substrate; two first deep trench capacitors disposed on the substrate outside the two active areas; a rectangular active word line disposed on the substrate covering the first deep trench capacitors and the active areas; first and second passing word lines disposed on one side of the rectangular active word line and across the parallel active areas; a third passing word line disposed on another side of the rectangular active word line and across another end of the two active areas; two second deep trench capacitors disposed on the substrate under where the two first passing word lines overlap the two active areas; and four contacts disposed on the first active areas between the first and second word lines and between the third and the rectangular active word line.
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公开(公告)号：US07217581B2
公开(公告)日：2007-05-15
申请号：US11339687
申请日：2006-01-26
IPC分类号： H01L21/00
CPC分类号： G03F9/7088 , G03F7/70633 , G03F7/70658 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.
摘要翻译： 提供了用于确定在集成电路制造工艺中发生的不对准的测试结构和测试方法。 测试结构包括具有第一测试结构和第二测试结构的第一导电层，其上的电介质层和介电层上的第二导电层。 第二导电层包括在第一方向和第二方向上分别与第一测试结构和第二测试结构的一部分重叠的第三测试结构和第四测试结构。 第一方向与第二方向相反。 该方法包括测量第一和第二导电层之间的电特性以计算由不对准引起的偏移量的步骤。
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8.发明授权Test key for validating the position of a word line overlaying a trench capacitor in DRAMs 有权用于验证在DRAM中覆盖沟槽电容器的字线的位置的测试键公开(公告)号：US06946678B2
公开(公告)日：2005-09-20
申请号：US10902450
申请日：2004-07-29
申请人： Tie Jiang Wu , Chien-Chang Huang , Yu-Wei Ting , Bo Ching Jiang
发明人： Tie Jiang Wu , Chien-Chang Huang , Yu-Wei Ting , Bo Ching Jiang
IPC分类号： G11C8/14 , H01L21/8242 , H01L23/544 , H01L27/02 , H01L23/58
CPC分类号： H01L27/10861 , G11C8/14 , H01L22/34 , H01L27/0207 , H01L27/1087 , H01L27/10891
摘要： A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.
摘要翻译： 用于验证覆盖DRAM的深沟槽电容器的字线结构的位置的测试键。 测试键被沉积在晶片的划线区域中。 深沟槽电容器沉积在划线区域并具有掩埋板。 在划线中沉积矩形字线并覆盖深沟槽电容器的一部分，并且在深沟槽上方沉积两条经过的字线。 第一掺杂区域和第二掺杂区域分别沉积在矩形字线和第一通过字线之间以及矩形字线和第二通过字线之间。 第一插头，第二插头和第三插头分别耦合到第一掺杂区域，第二掺杂区域和掩埋板。
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9.发明授权Device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices 有权用于检测DRAM器件中深沟槽电容器和有源区域的对准的装置和方法公开(公告)号：US06838296B2
公开(公告)日：2005-01-04
申请号：US10448920
申请日：2003-05-29
申请人： Tie-Jiang Wu , Chien-Chang Huang , Bo-Ching Jiang , Yu-Wei Ting
发明人： Tie-Jiang Wu , Chien-Chang Huang , Bo-Ching Jiang , Yu-Wei Ting
IPC分类号： H01L21/8242 , H01L23/544 , H01L27/02 , H01L21/66
CPC分类号： H01L27/10861 , G11C11/401 , G11C2029/5002 , H01L22/34 , H01L27/0207 , H01L27/10867 , H01L27/1087
摘要： A test device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices. A quadrilateral active area is disposed in the scribe line region, with four equilaterals and four vertex angles. Parallel first and second deep trench capacitors are disposed in the quadrilateral active area. The first deep trench capacitor has a first surface aligned with a second surface of the second deep trench capacitor. The first and second vertex angles of the four vertex angles have a diagonal line essentially perpendicular to the first and second surfaces. The first and second vertex angles are a predetermined distance from the first surface and the second surface respectively.
摘要翻译： 用于检测DRAM器件中深沟槽电容器和有源区域的对准的测试装置和方法。 四边形有源区域设置在划线区域，具有四个平衡和四个顶角。 平行的第一和第二深沟槽电容器设置在四边形有源区域中。 第一深沟槽电容器具有与第二深沟槽电容器的第二表面对准的第一表面。 四个顶角的第一和第二顶角具有基本上垂直于第一和第二表面的对角线。 第一和第二顶角分别与第一表面和第二表面预定的距离。
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10.发明授权Device and method for detecting alignment of active areas and memory cell structures in DRAM devices 有权用于检测DRAM器件中的有源区和存储单元结构的对准的装置和方法公开(公告)号：US07381575B2
公开(公告)日：2008-06-03
申请号：US11096836
申请日：2005-03-30
IPC分类号： H01L21/66
CPC分类号： H01L27/10876 , G11C11/401 , G11C29/36 , G11C2029/5002 , H01L22/34 , H01L27/10841
摘要： A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.
摘要翻译： 一种用于检测具有垂直晶体管的DRAM器件中的有源区和存储单元结构的对准的测试装置和方法。 在测试装置中，设置在划线区域中的并行第一和第二存储单元结构各自具有深沟槽电容器和晶体管结构。 有源区域设置在第一和第二存储单元结构之间。 活动区域与第一和第二存储单元结构重叠预定宽度。 第一和第二导电焊盘分别设置在第一存储单元结构的两端，第三和第四导电焊盘分别设置在第一存储单元结构的两端。
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