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    DYNAMIC RANDOM ACCESS MEMORY CELL LAYOUT AND FABRICATION METHOD THEREOF
    4.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY CELL LAYOUT AND FABRICATION METHOD THEREOF 审中-公开
    动态随机访问存储单元布局及其制造方法

    公开(公告)号：US20070152263A1

    公开(公告)日：2007-07-05

    申请号：US11687573

    申请日：2007-03-16

    申请人： Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

    发明人： Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yi-Nan Chen ,  Jeng-Ping Lin

    IPC分类号： H01L29/788

    CPC分类号： H01L27/1087 ,  H01L27/10832 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66181

    摘要： A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.

    摘要翻译： 用于布置深沟槽和有源区域的动态随机存取存储器（DRAM）单元布局及其制造方法。 有源区域包括两个垂直晶体管，一个常见的位线触点和两个深沟槽。 第一垂直晶体管形成在第一深沟槽与第一栅极导电线部分重叠的区域上。 第二垂直晶体管形成在第二深沟槽与第二栅极导电线部分重叠的区域上。

    Method for preventing leakage in shallow trench isolation
    5.
    发明授权
    Method for preventing leakage in shallow trench isolation 有权
    防止浅沟槽隔离泄漏的方法

    公开(公告)号：US07109094B2

    公开(公告)日：2006-09-19

    申请号：US10972506

    申请日：2004-10-25

    申请人： Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

    发明人： Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224

    摘要： Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

    摘要翻译： 浅沟槽隔离及其STI结构中防止潜行的方法。 提供具有形成在其上的焊盘层和沟槽的半导体衬底，随后在沟槽的侧壁上形成掺杂的第一衬里层。 然后在掺杂的第一衬里层上形成第二衬里层。 然后进行蚀刻以去除第一衬里层和第二衬里层的部分，使得第一衬里层的高度低于第二衬里层。 然后在焊盘层上形成牺牲层并填充沟槽。 然后进行扩散，使得第一衬里层中的掺杂离子扩散到衬底并在沟槽的两个底角之外形成漫射区。

    Shallow trench isolation structure
    6.
    发明授权
    Shallow trench isolation structure 有权
    浅沟隔离结构

    公开(公告)号：US06958521B2

    公开(公告)日：2005-10-25

    申请号：US10639419

    申请日：2003-08-11

    申请人： Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

    发明人： Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

    IPC分类号： H01L21/762 ,  H01L29/00

    CPC分类号： H01L21/76224

    摘要： Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

    摘要翻译： 浅沟槽隔离及其STI结构中防止潜行的方法。 提供具有形成在其上的焊盘层和沟槽的半导体衬底，随后在沟槽的侧壁上形成掺杂的第一衬里层。 然后在掺杂的第一衬里层上形成第二衬里层。 然后进行蚀刻以去除第一衬里层和第二衬里层的部分，使得第一衬里层的高度低于第二衬里层。 然后在焊盘层上形成牺牲层并填充沟槽。 然后进行扩散，使得第一衬里层中的掺杂离子扩散到衬底并在沟槽的两个底角之外形成漫射区。

    Trench-capacitor DRAM cell having a folded gate conductor
    7.
    发明授权
    Trench-capacitor DRAM cell having a folded gate conductor 有权
    具有折叠栅极导体的沟槽电容器DRAM单元

    公开(公告)号：US06909136B2

    公开(公告)日：2005-06-21

    申请号：US10604344

    申请日：2003-07-14

    申请人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Change-Rong Wu ,  Hui-Min Mao

    发明人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Change-Rong Wu ,  Hui-Min Mao

    IPC分类号： H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

    摘要： A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

    摘要翻译： 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

    Method for preventing sneakage in shallow trench isolation and STI structure thereof
    8.
    发明申请
    Method for preventing sneakage in shallow trench isolation and STI structure thereof 有权
    浅沟槽隔离及其STI结构中防止潜行的方法

    公开(公告)号：US20050127469A1

    公开(公告)日：2005-06-16

    申请号：US10972506

    申请日：2004-10-25

    申请人： Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

    发明人： Ming-Cheng Chang ,  Yi-Nan Chen ,  Jeng-Ping Lin

    IPC分类号： H01L21/762 ,  H01L21/20 ,  H01L21/76 ,  H01L29/00

    CPC分类号： H01L21/76224

    摘要： Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

    摘要翻译： 浅沟槽隔离及其STI结构中防止潜行的方法。 提供具有形成在其上的焊盘层和沟槽的半导体衬底，随后在沟槽的侧壁上形成掺杂的第一衬里层。 然后在掺杂的第一衬里层上形成第二衬里层。 然后进行蚀刻以去除第一衬里层和第二衬里层的部分，使得第一衬里层的高度低于第二衬里层。 然后在焊盘层上形成牺牲层并填充沟槽。 然后进行扩散，使得第一衬里层中的掺杂离子扩散到衬底并在沟槽的两个底角之外形成漫射区。

    TRENCH-CAPACITOR DRAM CELL HAVING A FOLDED GATE CONDUCTOR
    9.
    发明申请
    TRENCH-CAPACITOR DRAM CELL HAVING A FOLDED GATE CONDUCTOR 有权
    具有折叠门控导体的TRENCH-CAPACITOR DRAM单元

    公开(公告)号：US20050012131A1

    公开(公告)日：2005-01-20

    申请号：US10604344

    申请日：2003-07-14

    申请人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

    发明人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

    IPC分类号： H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

    摘要： A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

    摘要翻译： 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。